Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
3. The method of claim 2, wherein the first ESL comprises silicon nitride or silicon carbonitride.
This method describes forming a Magnetoresistive Random Access Memory (MRAM) device. The process involves embedding magneto-resistive memory cells with top electrodes into a dielectric layer, ensuring their top surfaces are coplanar with the dielectric. A first etch stop layer (ESL) is then applied over the dielectric; this first ESL specifically comprises silicon nitride (SiN) or silicon carbonitride (SiCN). A common electrode is formed, extending through this first ESL to directly contact the cell's top electrodes. Finally, a second etch stop layer is placed over the first ESL and the common electrode.
4. The method of claim 2, wherein the second ESL comprises aluminum oxide, zirconium oxide, or hafnium oxide.
This method details the fabrication of a Magnetoresistive Random Access Memory (MRAM) device. The process includes creating a dielectric layer, embedding magneto-resistive memory cells with top electrodes so their top surfaces are flush with the dielectric, and depositing a first etch stop layer (ESL) over the dielectric. A common electrode is then formed, extending through the first ESL to make direct contact with the top electrodes. Subsequently, a second etch stop layer is applied over the first ESL and the common electrode. This second etch stop layer is specifically composed of aluminum oxide (Al2O3), zirconium oxide (ZrO2), or hafnium oxide (HfO2).
5. The method of claim 2, wherein the first ESL comprises a thickness between about 50 Å and about 200 Å.
This method describes forming a Magnetoresistive Random Access Memory (MRAM) device by embedding magneto-resistive memory cells with top electrodes into a dielectric layer, ensuring their top surfaces are coplanar with the dielectric. A first etch stop layer (ESL) is deposited over the dielectric, with a precisely controlled thickness between approximately 50 Angstroms (Å) and 200 Angstroms (Å). A common electrode is then formed, extending through this first ESL to directly contact the top electrodes. Finally, a second etch stop layer is applied over both the first ESL and the common electrode.
6. The method of claim 2, wherein the second ESL comprises a thickness between about 20 Å and about 100 Å.
This method outlines the formation of a Magnetoresistive Random Access Memory (MRAM) device. It involves embedding magneto-resistive memory cells with top electrodes into a dielectric layer, ensuring their top surfaces are flush with the dielectric. A first etch stop layer (ESL) is deposited over the dielectric. A common electrode is then formed, extending through this first ESL to make direct contact with the cell's top electrodes. Subsequently, a second etch stop layer is applied over the first ESL and the common electrode, with this second ESL having a thickness optimized to be between approximately 20 Angstroms (Å) and 100 Angstroms (Å).
7. The method of claim 1, wherein a total thickness of the first ESL and the second ESL is between about 200 Å and about 300 Å.
This method describes forming a Magnetoresistive Random Access Memory (MRAM) device. The process involves embedding magneto-resistive memory cells with top electrodes into a dielectric layer, ensuring their top surfaces are flush with the dielectric. A first etch stop layer (ESL) is deposited over the dielectric. A common electrode is then formed, extending through this first ESL to directly contact the top electrodes. Subsequently, a second etch stop layer is placed over the first ESL and the common electrode. A key feature is that the combined total thickness of the first ESL and the second ESL is optimized to be between approximately 200 Angstroms (Å) and 300 Angstroms (Å).
8. The method of claim 1, wherein the common electrode comprises titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), or copper (Cu).
This method details the formation of a Magnetoresistive Random Access Memory (MRAM) device. The process involves creating a dielectric layer and embedding magneto-resistive memory cells with top electrodes, ensuring their top surfaces are coplanar with the dielectric. A first etch stop layer (ESL) is then deposited over the dielectric. A common electrode is formed, which extends through this first ESL to make direct electrical contact with the top electrodes of the memory cells. This common electrode can be composed of titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), or copper (Cu). A second etch stop layer is finally placed over the first ESL and the common electrode.
12. The method of claim 11, wherein a total thickness of the third ESL and the fourth ESL is between about 100 Å and about 200 Å.
This method describes a process for fabricating a semiconductor device that includes forming a third etch stop layer (ESL) and a fourth etch stop layer (ESL). A key characteristic of this method is that the combined total thickness of these two etch stop layers, the third ESL and the fourth ESL, is precisely controlled to be between approximately 100 Angstroms (Å) and 200 Angstroms (Å). This specific thickness optimization is crucial for achieving desired etching selectivity and process control during manufacturing.
13. The method of claim 11, wherein the third ESL comprises a thickness between about between about 20 Å and about 100 Å.
This method pertains to the fabrication of a semiconductor device. It involves forming specific layers, including a third etch stop layer (ESL) and a fourth etch stop layer (ESL). A particular feature of this method is that the third etch stop layer is deposited with a thickness maintained between approximately 20 Angstroms (Å) and 100 Angstroms (Å). This precise thickness control of the third ESL is important for effective process control and performance during the device manufacturing process.
14. The method of claim 11, wherein the fourth ESL comprises a thickness between about 10 Å and about 50 Å.
This method describes a process for manufacturing a semiconductor device. A key step involves forming a third etch stop layer (ESL) and a fourth etch stop layer (ESL) within the device structure. Notably, this method ensures that the fourth etch stop layer is applied with a thickness specifically designed to be between approximately 10 Angstroms (Å) and 50 Angstroms (Å). This precise thickness is critical for the layer's intended function, such as providing specific etch selectivity during subsequent processing steps.
18. The method of claim 17, wherein a thickness of the first etch stop layer is greater than a thickness of the second etch stop layer.
This method describes the fabrication of a Magnetoresistive Random Access Memory (MRAM) device. The process includes forming a dielectric layer, embedding magneto-resistive memory cells with top electrodes, and applying a first etch stop layer (ESL) over the dielectric. A common electrode is then created, extending through this first ESL to connect with the cell's top electrodes, followed by a second etch stop layer over the first ESL and common electrode. A distinctive feature of this method is that the thickness of the first etch stop layer is intentionally made greater than the thickness of the second etch stop layer.
20. The method of claim 19, wherein a thickness of the first nitrogen-containing layer is greater than a thickness of the second nitrogen-containing layer.
This method details a process for fabricating a semiconductor device. It involves forming at least two distinct layers: a first nitrogen-containing layer and a second nitrogen-containing layer. A key characteristic of this fabrication method is that the first nitrogen-containing layer is intentionally deposited or formed with a thickness that is greater than the thickness of the second nitrogen-containing layer. This controlled difference in thickness is critical for the layers' specific functionality within the device, such as acting as etch stops or as dielectric components.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 9, 2022
March 19, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.