A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, wherein the recessed portion of the second interconnect structure is directly connected to the first gate structure, and wherein the second interconnect structure further includes a non-recessed portion that is directly connected to the first portion of the first interconnect structure.
5. The semiconductor device of claim 4, wherein the second interconnect structure and the third interconnect structure are disposed in the same interconnect layer.
6. The semiconductor device of claim 4, wherein the first gate structure and the second gate structure are spaced apart from each other by a distance along the second lateral direction, and wherein a width by which at least the first portion or the second portion of the first interconnect structure is extended along the second lateral direction is equal to or greater than 1.5 times the distance.
7. The semiconductor device of claim 4, wherein the first gate structure and the second gate structure are adjacent ones of a number of gate structures that constitute a standard cell, the number being equal to or less than 5.
8. The semiconductor device of claim 1, wherein the first interconnect structure is included in one of a number of signal tracks disposed in an interconnect layer, the number being equal to or less than 3.
11. The semiconductor device of claim 10, wherein the recessed portion of the second interconnect structure is directly connected to the first gate structure.
12. The semiconductor device of claim 10, wherein the second interconnect structure further includes a non-recessed portion that is directly connected to the first portion of the first interconnect structure.
13. The semiconductor device of claim 10, wherein the first source/drain structure, the second source/drain structure, and the non-recessed portion of the second interconnect structure are substantially aligned with one another along the vertical direction.
14. The semiconductor device of claim 10, wherein the first transistor has a first conductive type, and the second transistor has a second conductive type opposite to the first conductive type.
15. The semiconductor device of claim 10, wherein each of the first gate structure and the second gate structure is one of a number of gate structures that constitute a standard cell, the number being equal to or less than 5.
16. The semiconductor device of claim 10, wherein the first interconnect structure is included in one of a number of signal tracks disposed in an interconnect layer, the number being equal to or less than 3.
18. The semiconductor device of claim 10, wherein the first transistor and second transistor collectively form a complementary field-effect transistor.
20. The semiconductor device of claim 19, wherein the first portion is shorter than the second portion, with respective bottom boundaries of the first and second portions substantially aligned with each other.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 8, 2022
March 26, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.