Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The memory system of claim 2, wherein the memory controller is to sense a current through the second select line according to a parallel resistance of i) a series resistance of the first memory cell and the second memory cell, and ii) a series resistance of the third memory cell and the fourth memory cell to read a multi-level data stored by the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell.
7. The memory system of claim 6, wherein the memory controller is to electrically float the first bit line and the second bit line to read a multi-level data stored by the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell.
18. The memory system of claim 17, wherein the memory controller is to sense a current through the second select line according to a parallel resistance of i) a series resistance of the first memory cell and the second memory cell, and ii) a series resistance of the third memory cell and the fourth memory cell to determine the multi-level data stored by the group of memory cells, while the first bit line and the second bit line are floated.
19. The memory system of claim 17, wherein the first select line, the second select line, the third select line, the first bit line, and the second bit line extend along a direction.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 28, 2022
April 2, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.