Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.
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3. The memory system of claim 2, wherein the memory controller is to sense a current through the second select line according to a parallel resistance of i) a series resistance of the first memory cell and the second memory cell, and ii) a series resistance of the third memory cell and the fourth memory cell to read a multi-level data stored by the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell.
This invention relates to a memory system designed to improve data storage and retrieval efficiency in multi-level memory cells. The system addresses the challenge of accurately reading multi-bit data stored in memory cells by leveraging parallel resistance configurations to enhance sensing precision. The memory system includes a memory controller connected to multiple memory cells arranged in a specific configuration. The controller senses current through a select line, which is influenced by the combined resistance of paired memory cells. Specifically, the system measures the parallel resistance formed by two series-connected memory cell pairs. This allows the controller to distinguish between different resistance states, enabling the accurate reading of multi-level data stored across the cells. The approach improves read accuracy by mitigating interference between adjacent cells and reducing the impact of process variations. The memory controller dynamically adjusts sensing parameters based on the detected resistance values, ensuring reliable data retrieval even in high-density memory arrays. This method enhances storage efficiency and performance in non-volatile memory systems, particularly those using resistive memory technologies.
7. The memory system of claim 6, wherein the memory controller is to electrically float the first bit line and the second bit line to read a multi-level data stored by the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell.
This invention relates to a memory system designed to improve data read operations in multi-level memory cells. The system addresses the challenge of accurately reading multiple bits stored in a single memory cell, which is increasingly difficult as memory densities increase and cell sizes shrink. The memory system includes a memory controller and a memory array with multiple memory cells connected to bit lines. The memory controller is configured to electrically float specific bit lines during read operations to enhance the accuracy of reading multi-level data. In particular, the controller floats a first bit line and a second bit line to read data stored by four memory cells connected to these lines. This floating technique reduces interference and noise, allowing the system to distinguish between different voltage levels representing multiple bits stored in each cell. The memory array is structured with memory cells arranged in a way that enables efficient multi-level data access, and the controller dynamically adjusts the bit line states to optimize read performance. This approach improves reliability and speed in high-density memory systems where traditional read methods may fail to accurately resolve multi-level data.
18. The memory system of claim 17, wherein the memory controller is to sense a current through the second select line according to a parallel resistance of i) a series resistance of the first memory cell and the second memory cell, and ii) a series resistance of the third memory cell and the fourth memory cell to determine the multi-level data stored by the group of memory cells, while the first bit line and the second bit line are floated.
This invention relates to memory systems, specifically those using multi-level memory cells where each cell stores multiple bits of data. A common challenge in such systems is accurately reading stored data due to variations in resistance paths within the memory cell array. The invention addresses this by providing a memory controller that senses current through a select line connected to a group of memory cells arranged in a specific configuration. The group includes at least four memory cells, with two pairs of cells connected in series and these pairs connected in parallel. The controller measures current through the select line while the bit lines connected to the memory cells are floated, allowing the resistance of the parallel and series combinations to influence the sensed current. By analyzing this current, the controller determines the multi-level data stored in the group of memory cells. This approach improves read accuracy by leveraging the resistance characteristics of the memory cell configuration without requiring active bit line connections during sensing. The method is particularly useful in high-density memory arrays where precise data retrieval is critical.
19. The memory system of claim 17, wherein the first select line, the second select line, the third select line, the first bit line, and the second bit line extend along a direction.
The invention relates to a memory system designed to improve data storage efficiency and access speed in semiconductor memory devices. The system addresses challenges in conventional memory architectures, such as limited scalability, high power consumption, and complex routing of interconnects, by optimizing the layout and arrangement of select lines and bit lines. The memory system includes multiple memory cells arranged in an array, where each memory cell is connected to a first select line, a second select line, a third select line, a first bit line, and a second bit line. These lines extend along a common direction, enabling efficient data access and reducing signal interference. The first and second select lines control the activation of memory cells, while the third select line provides additional control for enhanced functionality, such as multi-level data storage or improved error correction. The first and second bit lines facilitate data read and write operations, ensuring fast and reliable data transfer. The arrangement of these lines along a single direction simplifies the memory cell layout, reduces the footprint, and minimizes routing complexity. This design allows for higher memory density and improved performance, making it suitable for advanced semiconductor applications, including high-speed computing, data storage, and embedded systems. The system's modular structure enables easy integration with existing memory architectures, offering a scalable solution for future memory technologies.
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July 28, 2022
April 2, 2024
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