A method includes executing, by a processor core, a first task; scheduling, by a scheduler, a second task to be executed by the processor core upon completion of executing the first task; responsive to scheduling the second task, providing, by the scheduler, a prewarming message to a memory management unit (MMU) coupled to the processor core; and responsive to receiving the prewarming message, fetching, by the MMU, a page table specified by a page table base of the prewarming message.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the specified page table is stored in a main memory coupled to the MMU and the fetching further comprises caching the page table in a cache between the main memory and the processor core.
6. The method of claim 1, wherein the MMU receives the prewarming message directly from the scheduler.
7. The method of claim 1, wherein the processor core is a first processor core, the method further comprising executing, by a second processor core, a third task, wherein the scheduling of the second task to be executed by the first processor core upon completion of executing the first task is responsive to determining that the first processor core will complete executing the first task prior to the second processor core completing executing the third task.
9. The system of claim 8, further comprising a main memory coupled to the MMU and a cache between the main memory and the processor core, wherein the specified page table is stored in the main memory, and wherein the MMU is further configured to cache the page table in the cache.
13. The system of claim 8, wherein the MMU receives the prewarming message directly from the scheduler.
14. The system of claim 8, wherein the processor core is a first processor core, the system further comprising a second processor core configured to execute a third task, wherein the scheduler schedules the second task to be executed by the first processor core upon completion of executing the first task responsive to a determination that the first processor core will complete executing the first task prior to the second processor core completing executing the third task.
16. The non-transitory, computer-readable medium of claim 15, wherein the MMU is configured to couple to a main memory and to a cache between the main memory and the processor core, wherein the specified page table is stored in the main memory, and wherein the MMU is further configured to cache the page table in the cache.
20. The non-transitory, computer-readable medium of claim 15, wherein the instructions, when executed, cause the processor to provide the prewarming message directly to the MMU.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 12, 2020
April 9, 2024
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