Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
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2. The apparatus of claim 1, wherein the at least two copies of the instructions comprises a set of Basic Input/Output System (BIOS) code for the microprocessor.
This invention relates to a system for securely storing and executing firmware instructions, specifically targeting the protection of Basic Input/Output System (BIOS) code in computing devices. The problem addressed is the vulnerability of firmware to tampering, corruption, or unauthorized modification, which can compromise system integrity and security. The apparatus includes a microprocessor and a memory storing at least two copies of firmware instructions. The copies are stored in separate, non-overlapping memory regions to ensure redundancy and integrity verification. The microprocessor is configured to execute the instructions from one copy while comparing it against the other to detect discrepancies, such as errors or unauthorized changes. If a mismatch is found, the system can take corrective action, such as reverting to a known-good copy or triggering a security alert. The BIOS code, which initializes hardware during system startup, is particularly sensitive to tampering. By maintaining multiple copies, the system ensures that even if one copy is corrupted, the other can be used to restore functionality or verify the integrity of the primary copy. This redundancy mechanism enhances reliability and security, preventing malicious attacks or accidental corruption from disrupting system operations. The apparatus may also include additional features, such as cryptographic checks or access controls, to further protect the firmware from unauthorized access or modification.
3. The apparatus of claim 1, wherein the at least two copies of the instructions comprises a respective subset of a set of Basic Input/Output System (BIOS) code for the microprocessor.
The invention relates to a system for enhancing the reliability and security of a microprocessor by utilizing multiple copies of critical firmware instructions. The problem addressed is the vulnerability of a single copy of firmware code to corruption, tampering, or failure, which can lead to system instability or security breaches. The solution involves storing at least two copies of the firmware instructions, where each copy is a subset of the Basic Input/Output System (BIOS) code required for the microprocessor's operation. These copies are stored in separate memory locations to ensure redundancy and integrity. The apparatus includes a microprocessor and a memory storing the multiple copies of the BIOS code subsets. The use of multiple copies allows the system to detect and correct errors, ensuring that the microprocessor can reliably execute the necessary firmware instructions even if one copy becomes corrupted. This redundancy improves system resilience against hardware failures, software bugs, or malicious attacks targeting the firmware. The invention is particularly useful in environments where high reliability and security are critical, such as in servers, embedded systems, or mission-critical applications.
4. The apparatus of claim 1, wherein the set of memory arrays are configured to store, within the second subset of memory cells, the at least two copies of the instructions in association with a cyclic redundancy check, or an error correcting code, or both.
This invention relates to memory storage systems, specifically apparatuses for storing and retrieving data with enhanced reliability. The problem addressed is ensuring data integrity in memory arrays, particularly for critical instructions that must be accurately retrieved even in the presence of errors. The apparatus includes a set of memory arrays divided into subsets of memory cells. The second subset of these memory cells is configured to store at least two copies of instructions, along with error detection and correction mechanisms. These mechanisms include a cyclic redundancy check (CRC), an error correcting code (ECC), or a combination of both. The CRC provides a checksum to detect errors, while the ECC allows for the correction of detected errors. By storing multiple copies of the instructions with these error-handling codes, the system improves fault tolerance and data reliability. The apparatus ensures that even if one copy of the instructions is corrupted, the other copies and error codes can be used to reconstruct the original data accurately. This approach is particularly useful in systems where data integrity is critical, such as in embedded systems, storage devices, or mission-critical applications.
10. The method of claim 8, wherein the two or more copies of the instructions comprises a set of Basic Input/Output System (BIOS) code for the microprocessor.
The invention relates to a method for managing multiple copies of executable instructions in a computing system, particularly focusing on Basic Input/Output System (BIOS) code for a microprocessor. The method addresses the challenge of ensuring system reliability and security by maintaining redundant copies of critical firmware instructions, such as BIOS code, to prevent failures or corruption from compromising system functionality. The method involves storing two or more copies of the BIOS code in separate memory locations or storage devices. These copies are synchronized to ensure consistency, allowing the system to detect and recover from errors by switching to an uncorrupted copy if one becomes damaged or compromised. The method may include verifying the integrity of each copy, such as through checksums or cryptographic hashes, to confirm their validity before execution. If a copy is found to be invalid, the system automatically selects an alternative valid copy to maintain operational continuity. The method may also include updating the BIOS code across all copies simultaneously to ensure synchronization. This prevents discrepancies between copies that could lead to errors or security vulnerabilities. The approach is particularly useful in environments where system uptime and security are critical, such as in servers, embedded systems, or mission-critical applications. By maintaining redundant, synchronized copies of BIOS code, the method enhances system resilience against hardware failures, software corruption, or malicious attacks.
11. The method of claim 8, wherein the two or more copies of the instructions comprises a respective subset of a set of Basic Input/Output System (BIOS) code for the microprocessor.
A method for managing multiple copies of instructions in a computing system, particularly for Basic Input/Output System (BIOS) code execution. The method addresses the challenge of ensuring reliable and secure execution of critical system-level instructions by maintaining redundant copies of BIOS code segments. Each copy is stored in separate memory locations or devices to prevent single-point failures. The method involves selecting a subset of the BIOS code for duplication, storing these subsets across multiple memory locations, and executing them in a controlled manner to verify integrity and functionality. This redundancy improves fault tolerance, allowing the system to recover from errors or corruption in one copy by falling back to another. The approach is particularly useful in systems where BIOS integrity is critical, such as embedded systems, servers, or high-availability computing environments. The method ensures that even if one copy of the BIOS code is compromised or fails, the system can still operate using an alternative copy, maintaining stability and security. The technique may also include validation steps to confirm the correctness of the redundant copies before execution.
18. The apparatus of claim 16, wherein the first copy and the second copy of the instructions comprises a set of Basic Input/Output System (BIOS) code for the microprocessor.
The invention relates to a system for managing and executing instructions in a computing environment, specifically addressing the need for reliable and secure execution of critical system code. The apparatus includes a microprocessor and a memory storing a first copy and a second copy of instructions, where the microprocessor is configured to execute the instructions from the first copy and verify the integrity of the second copy. The verification process ensures that the second copy remains unaltered, providing a fallback mechanism if the first copy is compromised or corrupted. This dual-copy approach enhances system stability and security by allowing the microprocessor to detect and recover from errors in the primary instruction set. The instructions stored in the memory are specifically Basic Input/Output System (BIOS) code, which is essential for initializing hardware components during the boot process. By maintaining redundant copies of the BIOS code, the system ensures that critical low-level operations remain functional even if one copy is damaged or tampered with. The apparatus may also include additional features, such as error correction mechanisms or secure storage, to further protect the integrity of the instruction copies. This design is particularly useful in environments where system reliability and security are paramount, such as in embedded systems, servers, or mission-critical applications.
19. The apparatus of claim 16, wherein the first copy and the second copy of the instructions comprises a respective subset of a set of Basic Input/Output System (BIOS) code for the microprocessor.
This invention relates to a system for managing and executing Basic Input/Output System (BIOS) code in a microprocessor-based computing environment. The problem addressed is ensuring reliable and secure execution of BIOS code, particularly in systems where multiple copies of the code may be stored or processed. The apparatus includes a microprocessor and a memory storing instructions for execution by the microprocessor. The memory contains at least two copies of the BIOS code, where each copy is a subset of the full BIOS code set. These subsets may be distributed across different memory locations or modules to enhance redundancy, fault tolerance, or security. The apparatus may also include mechanisms to verify the integrity of the BIOS code subsets before execution, ensuring that only valid and uncorrupted instructions are processed. This approach allows for modular execution of BIOS functions, reducing the risk of system failure due to corrupted or incomplete BIOS code. The system may further include error detection and recovery mechanisms to handle discrepancies between the subsets, ensuring consistent and reliable system operation. The use of multiple subsets enables selective execution of specific BIOS functions, improving efficiency and security in the boot process.
20. The apparatus of claim 16, wherein the first copy and the second copy of the instructions is associated with a cyclic redundancy check, or error correcting codes, or both.
This invention relates to data storage systems, specifically addressing the need for reliable data integrity and error detection in redundant storage configurations. The apparatus includes a storage system that maintains at least two copies of instructions or data, ensuring redundancy to prevent data loss. The first and second copies are stored in separate locations to mitigate the risk of simultaneous failure. To further enhance reliability, each copy is associated with a cyclic redundancy check (CRC), error correcting codes (ECC), or both. The CRC provides a checksum to detect errors in the stored data, while the ECC allows for the correction of detected errors, improving data accuracy. The system may also include mechanisms to verify the integrity of the stored copies by comparing the CRC or ECC values, ensuring that any discrepancies are identified and corrected. This approach is particularly useful in environments where data integrity is critical, such as in enterprise storage systems, backup solutions, or distributed computing architectures. The use of redundancy combined with error detection and correction ensures that data remains accurate and accessible even in the presence of hardware failures or data corruption.
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August 10, 2022
April 9, 2024
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