A system includes a high-bandwidth inter-chip network (ICN) that allows communication between parallel processing units (PPUs) in the system. For example, the ICN allows a PPU to communicate with other PPUs on the same compute node or server and also with PPUs on other compute nodes or servers. In embodiments, communication may be at the command level (e.g., at the direct memory access level) and at the instruction level (e.g., the finer-grained load/store instruction level). The ICN allows PPUs in the system to communicate without using a PCIe bus, thereby avoiding its bandwidth limitations and relative lack of speed. The respective routing tables comprise information of multiple paths to any given other PPU.
Legal claims defining the scope of protection, as filed with the USPTO.
2. A processing system of claim 1, wherein the routing tables are stored in registers associated with the plurality of processing units.
3. A processing system of claim 2, wherein the routing tables are re-configurable.
4. A processing system of claim 1, wherein the routing tables are compatible with a basic X-Y routing scheme.
6. A processing system of claim 5, wherein the respective routing tables comprise information of a next PPU in a routing sequence.
7. A system of claim 1, wherein the PPU is included in a first set of the plurality of PPUs and the first set of the plurality of PPUs is included in a first compute node, and a second set of the plurality of PPUs is included in a second node of the plurality of PPUs.
8. A system of claim 5, wherein the respective ones of the plurality of parallel processing units include respective ones of the routing tables.
9. A system of claim 5, a respective one of a plurality of parallel processing units is considered a source PPU when a communication originates at the respective one of a plurality of parallel processing units, a relay PPU when a communication passes through the respective one of a plurality of parallel processing units, or a destination PPU when a communication ends at the respective one of a plurality of parallel processing units.
10. A system of claim 7, wherein respective ones of the plurality of interconnects are configured for multi-flow balancing, wherein the source PPU supports parallel communication flows up to a maximum number of links between the source PPU and the destination PPU.
11. A system of claim 7, wherein respective ones of the plurality of interconnects are configured for many-flow balancing, wherein a relay PPU runs routing to balance flows among egresses.
17. A system of claim 15, wherein the plurality of processing units communicates over the plurality of interconnects and corresponding communications are configured in accordance with routing tables, wherein the routing tables are static and predetermined, wherein the routing tables are loaded in registers associated with the plurality of processing units as part of a setup of the plurality of processors before running normal processing operations, and wherein the routing tables include indications of multiple links between a source and a destination.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 15, 2022
April 16, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.