A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack comprising a plurality of dielectric layer pairs disposed over a substrate; forming a first mask stack over the alternating layer stack; patterning the first mask stack to define a staircase region comprising a number of N sub-staircase regions over the alternating layer stack using a lithography process and N is greater than 1; forming a first staircase structure over the staircase region, the first staircase structure has a number of M steps at each of the staircase regions and M is greater than 1; and forming a second staircase structure on the first staircase structure, the second staircase structure has a number of 2*N*M steps at the staircase region.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory device of claim 1, wherein each of the two or more sub-staircase structures comprises staircase steps, each of the staircase steps corresponding to a different conductor layer in the alternating layer stack.
3. The memory device of claim 2, wherein each of the two or more sub-staircase structures comprises an even number of the staircase steps.
4. The memory device of claim 2, wherein a top-most staircase step of each of the two or more sub-staircase structures is in a center of each of the two or more sub-staircase structures.
5. The memory device of claim 2, wherein a bottom-most staircase step of each of the two or more sub-staircase structures is in a center of each of the two or more sub-staircase structures.
6. The memory device of claim 1, wherein the staircase structure further comprises the two or more sub-staircase structures in a third direction perpendicular to the first direction and the second direction.
7. The memory device of claim 1, wherein the storage structure further comprises memory cells stacked in the first direction and formed at intersections between the semiconductor channel and conductor layers of the alternating layer stack.
8. The memory device of claim 1, wherein the insulating layer comprises silicon oxide, aluminum oxide, or a combination thereof.
9. The memory device of claim 1, wherein the conductor layer comprises tungsten, poly-crystalline silicon, silicide, nickel, titanium, platinum, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.
11. The memory device of claim 1, wherein the staircase structure further comprises a slit separating the two or more sub-staircase structures.
13. The memory device of claim 12, wherein a top-most staircase step of the 2*M number of staircase steps is in a center of the at least one of the N number of sub-staircase structures.
14. The memory device of claim 12, wherein a bottom-most staircase step of the 2*M number of staircase steps is in a center of the at least one of the N number of sub-staircase structures.
15. The memory device of claim 12, wherein each of the conductor/dielectric layer pairs comprises an insulating layer and a conductor layer.
16. The memory device of claim 15, wherein the insulating layer comprises silicon oxide, aluminum oxide, or a combination thereof.
17. The memory device of claim 15, wherein the conductor layer comprises tungsten, poly-crystalline silicon, silicide, nickel, titanium, platinum, aluminum, titanium nitride, tantalum nitride, tungsten nitride, or a combination thereof.
18. The memory device of claim 15, wherein the storage structure further comprises a memory cell formed at an intersection between the vertical semiconductor channel and the conductor layer.
20. The memory device of claim 12, wherein the staircase structure comprises 2*M*N number of staircase steps, each corresponding to a different conductor/dielectric layer pair.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 5, 2022
April 16, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.