A compact inverter system includes a bus bar. The bus bar includes a terminal for connection to a positive terminal of a DC voltage supply. The compact inverter also includes a heat sink, a first transistor, and a second transistor. The first transistor has first and second terminals between which current is transmitted when the first transistor is activated, and a first gate terminal controlling the first transistor. The first terminal of the first transistor is thermally and electrically connected to the bus bar. The second transistor has first and second terminals between which current is transmitted when the second transistor is activated, and a second gate terminal controlling the second transistor. The first terminal of the second transistor is thermally and electrically connected to the heat sink. The first and second transistors are positioned between the bus bar and the heat sink. The first transistor is positioned between the second transistor and the bus bar. The second transistor is positioned between the first transistor and the heat sink.
Legal claims defining the scope of protection, as filed with the USPTO.
6. The power inverter of claim 5 wherein the cylindrical channel comprises a wall, and wherein the solid dielectric layer contacts the wall.
7. The power inverter of claim 4 wherein the first and second transistors are positioned in first and second planes, respectively, and wherein the first and second planes are parallel to each other and positioned between the bus bar and the first heat sink.
8. The power inverter of claim 7 wherein no dielectric exists between the first terminal of the first transistor and the bus bar, and no dielectric exists between the first terminal of the second transistor and the first heat sink.
10. The power inverter of claim 9 wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the bus bar are positioned between the first and second heat sinks.
15. The power inverter of claim 14 wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the bus bar are positioned between the first and second heat sinks.
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March 4, 2021
April 23, 2024
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