Disclosed herein is an apparatus that includes a clock generator configured to generate first to fourth clock signals based on an input clock signal, a first duty-cycle detector configured to output a first signal responsive to a comparison between information produced based on the first and second clock signals and based on the third and fourth clock signals, a second duty-cycle detector configured to output a second signal responsive to a comparison between information produced based on the first and fourth clock signals and based on the second and third clock signals, a third duty-cycle detector configured to output a third signal responsive to a comparison between information produced based on the first and third clock signals and based on the second and fourth clock signals, and a duty-cycle adjuster configured to adjust a duty-cycle of the input clock signal responsive to the first to third signals.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The apparatus as claimed in claim 3, further comprising an analyzing circuit configured to analyze the first, second, and third detection signals to update the first, second, third, and fourth count values.
5. The apparatus as claimed in claim 4, wherein the analyzing circuit is configured to increment or decrement the first, second, third, and fourth counter circuits by a first step during a first operation stage and increment or decrement the first, second, third, and fourth counter circuits in a second step smaller than the first step during a second operation stage subsequent to the first operation stage.
6. The apparatus as claimed in claim 5, wherein an operation stage of the analyzing circuit is changed from the first operation stage to the second operation stage when transitions of the first, second, and third detection signals are occurred.
7. The apparatus as claimed in claim 6, wherein the operation stage of the analyzing circuit is changed from the first operation stage to the second operation stage when one or two of the first, second, and third detection signals oscillate while remaining one or two of the first, second, and third detection signals is fixed.
8. The apparatus as claimed in claim 4, wherein the analyzing circuit is configured to detect a longest or shortest one of the first, second, third, and fourth periods by analyzing the first, second, and third detection signals.
9. The apparatus as claimed in claim 8, wherein the analyzing circuit is configured to, when detecting the first period is the longest one, increment the first counter circuit to increase a delay of the rising edge of the first input clock signal or decrement the third counter circuit to decrease a delay of the rising edge of the second input clock signal.
10. The apparatus as claimed in claim 9, wherein the analyzing circuit is configured to, when detecting the first period is the shortest one, increment the third counter circuit to increase a delay of the rising edge of the second input clock signal or decrement the first counter circuit to decrease a delay of the rising edge of the first input clock signal.
11. The apparatus as claimed in claim 10, wherein the analyzing circuit is configured to, when detecting the second period is the longest one, increment the third counter circuit to increase a delay of the rising edge of the second input clock signal or decrement the second counter circuit to decrease a delay of the falling edge of the first input clock signal.
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June 21, 2022
April 30, 2024
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