Disclosed herein is an apparatus that includes a clock generator configured to generate first to fourth clock signals based on an input clock signal, a first duty-cycle detector configured to output a first signal responsive to a comparison between information produced based on the first and second clock signals and based on the third and fourth clock signals, a second duty-cycle detector configured to output a second signal responsive to a comparison between information produced based on the first and fourth clock signals and based on the second and third clock signals, a third duty-cycle detector configured to output a third signal responsive to a comparison between information produced based on the first and third clock signals and based on the second and fourth clock signals, and a duty-cycle adjuster configured to adjust a duty-cycle of the input clock signal responsive to the first to third signals.
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4. The apparatus as claimed in claim 3, further comprising an analyzing circuit configured to analyze the first, second, and third detection signals to update the first, second, third, and fourth count values.
This invention relates to an apparatus for detecting and analyzing signals in a system, particularly for monitoring and updating count values based on detected signals. The apparatus includes a detection circuit that generates first, second, and third detection signals corresponding to different conditions or events in the system. These signals are processed to update first, second, third, and fourth count values, which track occurrences of specific events or states. The apparatus further includes an analyzing circuit that evaluates the detection signals to refine or adjust the count values, ensuring accurate tracking of system behavior. The detection circuit may use multiple sensors or signal sources to generate the detection signals, which are then processed to increment or decrement the count values based on predefined criteria. The analyzing circuit may apply algorithms or logic to validate the detection signals and ensure the count values reflect the true state of the system. This apparatus is useful in applications requiring precise monitoring of system events, such as industrial control systems, safety mechanisms, or diagnostic tools. The invention improves reliability by dynamically updating count values based on real-time signal analysis, reducing errors in event tracking.
5. The apparatus as claimed in claim 4, wherein the analyzing circuit is configured to increment or decrement the first, second, third, and fourth counter circuits by a first step during a first operation stage and increment or decrement the first, second, third, and fourth counter circuits in a second step smaller than the first step during a second operation stage subsequent to the first operation stage.
This invention relates to an apparatus for analyzing signals, particularly in systems requiring precise signal processing with adjustable resolution. The apparatus includes multiple counter circuits and an analyzing circuit that controls their operation in distinct stages to improve accuracy and efficiency. The analyzing circuit adjusts the counter circuits by incrementing or decrementing them in two stages. During the first stage, the counters are adjusted by a larger step size, allowing for rapid initial adjustments. In the second stage, which follows the first, the counters are adjusted by a smaller step size, enabling finer adjustments for precise signal analysis. This two-stage approach balances speed and accuracy, making the apparatus suitable for applications requiring high-resolution signal processing, such as digital signal processing, communication systems, or measurement instruments. The invention improves upon prior systems by dynamically adjusting the step size, reducing errors and enhancing performance in signal analysis tasks.
6. The apparatus as claimed in claim 5, wherein an operation stage of the analyzing circuit is changed from the first operation stage to the second operation stage when transitions of the first, second, and third detection signals are occurred.
The invention relates to an apparatus with an analyzing circuit that operates in multiple stages to process detection signals. The apparatus is designed to monitor and analyze transitions in three distinct detection signals, which may originate from sensors or other input sources. The analyzing circuit initially operates in a first operation stage, where it performs a baseline or initial analysis of the detection signals. When specific transitions occur in all three detection signals simultaneously, the analyzing circuit switches to a second operation stage. This transition triggers a change in the circuit's behavior, enabling it to perform a different or more advanced analysis. The second operation stage may involve enhanced processing, additional computations, or different signal interpretation compared to the first stage. The apparatus ensures that the transition between stages is synchronized with the detection signal transitions, ensuring accurate and timely analysis. This design is useful in systems requiring adaptive or multi-stage signal processing, such as environmental monitoring, industrial control, or safety systems where dynamic response to signal changes is critical. The apparatus improves reliability and responsiveness by dynamically adjusting its operation based on real-time signal conditions.
7. The apparatus as claimed in claim 6, wherein the operation stage of the analyzing circuit is changed from the first operation stage to the second operation stage when one or two of the first, second, and third detection signals oscillate while remaining one or two of the first, second, and third detection signals is fixed.
The invention relates to an apparatus for analyzing signals, particularly in systems where multiple detection signals are monitored for changes in their behavior. The problem addressed is the need to dynamically adjust the operation of an analyzing circuit based on the behavior of multiple detection signals, ensuring accurate and adaptive signal processing. The apparatus includes an analyzing circuit configured to operate in at least two distinct operation stages. The circuit monitors three detection signals—first, second, and third—each representing different parameters or conditions in a system. The analyzing circuit transitions from a first operation stage to a second operation stage when one or two of the detection signals exhibit oscillatory behavior, while the remaining one or two signals remain fixed or stable. This transition allows the apparatus to adapt its processing based on the dynamic changes in the detection signals, improving system responsiveness and accuracy. The first operation stage may involve a baseline or default mode of operation, while the second operation stage could implement a modified or enhanced processing mode. The transition is triggered by detecting oscillations in one or two signals while the others remain constant, ensuring that the apparatus responds only to meaningful changes rather than noise or transient fluctuations. This adaptive behavior is particularly useful in applications where signal stability is critical, such as in sensor networks, industrial control systems, or medical monitoring devices. The apparatus ensures reliable operation by dynamically adjusting its processing logic in response to real-time signal conditions.
8. The apparatus as claimed in claim 4, wherein the analyzing circuit is configured to detect a longest or shortest one of the first, second, third, and fourth periods by analyzing the first, second, and third detection signals.
The invention relates to an apparatus for analyzing periodic signals, particularly in systems where multiple periodic signals are present and need to be distinguished based on their duration. The problem addressed is the need to accurately identify the longest or shortest period among multiple periodic signals in a reliable and efficient manner. The apparatus includes an analyzing circuit that receives three detection signals, each corresponding to a different periodic signal. These detection signals are derived from four distinct periodic signals, where the first, second, third, and fourth periods are associated with these signals. The analyzing circuit is configured to process the first, second, and third detection signals to determine the longest or shortest period among the four. This involves comparing the durations of the periods represented by the detection signals to identify the extreme value (either the longest or shortest) based on predefined criteria. The apparatus may be used in applications such as signal processing, communication systems, or industrial monitoring, where distinguishing between different periodic signals is critical for system performance. The analyzing circuit ensures accurate detection by leveraging the relationships between the detection signals, allowing for precise identification of the desired period.
9. The apparatus as claimed in claim 8, wherein the analyzing circuit is configured to, when detecting the first period is the longest one, increment the first counter circuit to increase a delay of the rising edge of the first input clock signal or decrement the third counter circuit to decrease a delay of the rising edge of the second input clock signal.
This invention relates to clock synchronization circuits, specifically addressing phase alignment between two input clock signals. The problem solved is ensuring precise timing alignment between clock signals in digital systems, where mismatched phases can cause data transmission errors or system malfunctions. The apparatus includes a phase detector circuit that compares the phases of a first and second input clock signal to determine their relative timing. An analyzing circuit evaluates the phase difference and identifies the longest period between phase transitions. If the first clock signal's period is the longest, the analyzing circuit adjusts the delay of the rising edge of the first clock signal by incrementing a first counter circuit, which increases the delay. Alternatively, it may decrement a third counter circuit to decrease the delay of the second clock signal's rising edge. These adjustments are made to align the phases of the two clock signals more closely, reducing phase misalignment errors. The apparatus also includes a second counter circuit that, when the second clock signal's period is the longest, adjusts the delay of the first clock signal's rising edge by decrementing the first counter circuit or incrementing the third counter circuit to increase the delay of the second clock signal. This ensures bidirectional phase correction, allowing the system to dynamically compensate for phase differences in either direction. The counter circuits provide fine-grained control over the delay adjustments, enabling precise phase alignment.
10. The apparatus as claimed in claim 9, wherein the analyzing circuit is configured to, when detecting the first period is the shortest one, increment the third counter circuit to increase a delay of the rising edge of the second input clock signal or decrement the first counter circuit to decrease a delay of the rising edge of the first input clock signal.
This invention relates to clock synchronization circuits, specifically addressing the challenge of aligning the rising edges of two input clock signals to minimize phase differences. The apparatus includes a phase detector that compares the phases of the first and second input clock signals, generating a phase difference signal. An analyzing circuit evaluates this signal to determine the shortest period between the rising edges of the two clocks. If the first clock's rising edge leads the second clock's rising edge by the smallest interval, the analyzing circuit adjusts the delay of the first clock's rising edge by decrementing a first counter circuit, effectively advancing the phase. Conversely, if the second clock's rising edge leads the first by the smallest interval, the analyzing circuit increments a third counter circuit to delay the second clock's rising edge. These adjustments are made iteratively to fine-tune the phase alignment, ensuring precise synchronization between the two clock signals. The system dynamically compensates for phase discrepancies, improving timing accuracy in digital circuits where synchronized clock signals are critical.
11. The apparatus as claimed in claim 10, wherein the analyzing circuit is configured to, when detecting the second period is the longest one, increment the third counter circuit to increase a delay of the rising edge of the second input clock signal or decrement the second counter circuit to decrease a delay of the falling edge of the first input clock signal.
This invention relates to clock synchronization circuits, specifically addressing phase alignment between two input clock signals. The problem solved is ensuring precise timing alignment by dynamically adjusting the phase relationship between the rising edge of a second input clock signal and the falling edge of a first input clock signal. The apparatus includes a phase detector circuit that compares the phase difference between the two clock signals and identifies the longest period between specific edges of these signals. An analyzing circuit evaluates this phase difference and adjusts delay circuits to correct misalignment. When the second period (the interval between the rising edge of the second clock and the falling edge of the first clock) is determined to be the longest, the analyzing circuit either increments a third counter circuit to increase the delay of the second clock's rising edge or decrements a second counter circuit to reduce the delay of the first clock's falling edge. These adjustments are made to minimize phase error and maintain synchronization. The system ensures stable clock alignment by dynamically compensating for phase deviations, improving performance in high-speed digital circuits where precise timing is critical.
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June 21, 2022
April 30, 2024
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