Apparatuses, systems, and techniques for memory management are disclosed. In at least one embodiment, memory management is provided for a heterogenous system, for example, a system including a CPU and a GPU, in which redundant or unnecessary memory transfers are reduced.
Legal claims defining the scope of protection, as filed with the USPTO.
5. The method of claim 4, wherein the predetermined condition comprises receiving an instruction to map the virtual memory address to the second physical memory address.
11. The method of claim 10, wherein the predetermined condition comprises a data storage comprising the physical memory experiencing at least a threshold amount of memory pressure.
19. The system of claim 18, wherein the virtual memory address is mapped to the second physical memory address in response to the second processor accessing the virtual memory address.
22. The system of claim 21, wherein the predetermined condition comprises receiving an instruction to map the virtual memory address to the second physical memory address, in response to the second processor accessing the virtual memory address.
26. The system of claim 25, wherein the condition comprises a data storage comprising the physical memory experiencing memory pressure.
33. The circuit of claim 32, wherein the predetermined condition comprises a processor associated with the second physical memory address accessing the virtual memory address.
36. The circuit of claim 35, wherein the condition comprises a data storage comprising the physical memory experiencing memory pressure.
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July 19, 2022
May 7, 2024
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