A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The manufacturing method of the semiconductor structure according to claim 1, wherein a shape of the non-merged spacer in a top view comprises a U shape.
3. The manufacturing method of the semiconductor structure according to claim 1, wherein the line width of the merged spacer is greater than one time of the line width of the non-merged spacer, and less than or equal to twice the line width of the non-merged spacer.
4. The manufacturing method of the semiconductor structure according to claim 1, wherein there is a first opening between the two adjacent first cores, and there is a second opening between the two adjacent second cores.
5. The manufacturing method of the semiconductor structure according to claim 4, wherein the first opening is connected to the second opening.
6. The manufacturing method of the semiconductor structure according to claim 4, wherein a width of the first opening is less than a width of the second opening.
7. The manufacturing method of the semiconductor structure according to claim 4, wherein a width of the first opening is greater than one time of a thickness of the spacer material layer and less than or equal to twice the thickness of the spacer material layer.
8. The manufacturing method of the semiconductor structure according to claim 7, wherein adjacent portions of the spacer material layer located on a sidewall of the first opening are merged together.
9. The manufacturing method of the semiconductor structure according to claim 4, wherein a width of the second opening is greater than twice a thickness of the spacer material layer.
10. The manufacturing method of the semiconductor structure according to claim 9, wherein the spacer material layer does not completely fill the second opening.
11. The manufacturing method of the semiconductor structure according to claim 1, wherein the first patterned mask layer extends in a first direction, and the merged spacer extends in a second direction, wherein the second direction intersects the first direction.
13. The manufacturing method of the semiconductor structure according to claim 12, wherein a shape of the branch portion in a top view comprises a two-pronged shape.
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June 8, 2023
May 7, 2024
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