A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.
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2. The semiconductor device of claim 1, wherein at least a portion of the connection side surface is disposed on the same level as a level of an upper surface of at least one of the memory vertical structure, the supporter vertical structure, and the first dam vertical structure.
The invention relates to semiconductor devices, specifically those incorporating memory vertical structures, supporter vertical structures, and dam vertical structures. The problem addressed involves optimizing the arrangement of these structures to improve device performance and reliability. The semiconductor device includes a substrate with multiple vertical structures formed thereon. The memory vertical structures are configured to store data, while the supporter vertical structures provide mechanical support. The first dam vertical structure acts as a barrier to prevent unwanted material diffusion or structural deformation during fabrication or operation. A key feature of the invention is the alignment of at least a portion of the connection side surface of these vertical structures. This surface is positioned at the same level as the upper surface of at least one of the memory, supporter, or dam vertical structures. This alignment ensures uniform electrical connections, reduces manufacturing defects, and enhances overall device stability. The precise leveling of these surfaces facilitates consistent interconnections between the vertical structures and other components, such as interconnect layers or peripheral circuits. The invention improves integration density and operational efficiency in semiconductor devices, particularly in advanced memory technologies like 3D NAND or other high-density storage solutions. The alignment of the connection side surface with the upper surfaces of the vertical structures ensures reliable electrical and mechanical coupling, minimizing misalignment-induced failures. This design is particularly useful in high-performance semiconductor applications where precision and reliability are critical.
16. The semiconductor device of claim 15, wherein a length of the void in the separation gap-fill material layer in a vertical direction is greater than a length of the void in the gap-fill insulating layer of at least one of the memory vertical structure, the supporter vertical structure, and the dam vertical structure in the vertical direction.
This invention relates to semiconductor devices, specifically those with vertical structures such as memory, supporter, and dam vertical structures. The problem addressed is the formation of voids in gap-fill insulating layers during semiconductor fabrication, which can degrade device performance and reliability. The invention improves upon prior art by controlling the void formation in a separation gap-fill material layer to enhance structural integrity and electrical isolation. The semiconductor device includes multiple vertical structures embedded in a substrate, each surrounded by a gap-fill insulating layer. A separation gap-fill material layer is formed adjacent to these structures, containing voids that are intentionally designed to have a greater vertical length than the voids in the gap-fill insulating layers of the vertical structures. This configuration ensures that the separation layer maintains superior isolation properties while minimizing defects. The voids in the separation layer are engineered to prevent electrical leakage and mechanical stress, which are critical for high-density semiconductor devices. The invention also includes methods to precisely control the deposition and etching processes to achieve the desired void dimensions, ensuring consistent performance across the device. This approach improves yield and reliability in advanced semiconductor manufacturing, particularly for memory and logic devices.
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June 9, 2021
May 7, 2024
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