A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, wherein at least a portion of the connection side surface is disposed on the same level as a level of an upper surface of at least one of the memory vertical structure, the supporter vertical structure, and the first dam vertical structure.
16. The semiconductor device of claim 15, wherein a length of the void in the separation gap-fill material layer in a vertical direction is greater than a length of the void in the gap-fill insulating layer of at least one of the memory vertical structure, the supporter vertical structure, and the dam vertical structure in the vertical direction.
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June 9, 2021
May 7, 2024
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