Exemplary embodiments for a multiprocessor pipeline architecture that converts signals from sequencing sample acquisition into sequence data, comprising: a custom coprocessor card configured to directly receive a stream of serialized sensor data generated by an image sensor, wherein the sensor data represents frame-by-frame intensity values for pixels comprising the image sensor, wherein the image sensor captures images of light emitted from a plurality of reaction cells of a removable integrated sequencing chip; a first coprocessor that continually receives the stream of serialized sensor data and transposes the frame-by-frame intensity values into reaction cell chunks, each of the reaction cell chunks representing movie data of the pixel intensity values of a corresponding reaction cell across the frames over a predetermined time window; a buffer that repeatedly receives the reaction cell chunks and stores in contiguous memory locations the reaction cell chunks for each respective reaction cell over a larger predetermined time window to create larger reaction cell chunks; and a plurality of second coprocessors that retrieve the larger reaction cell chunks from the buffer and convert, in parallel, the pixel intensity values into base-by-base sequence data even as additional reaction cell chunks are received by the buffer, such that the second coprocessors begin raw base calling before all the sensor data for the sequencing sample acquisition is obtained. Aspects of the invention include methods for base calling using single instruction multiple data vector processing units.
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2. The computer system of claim 1, wherein the primary analysis coprocessor card is configured with a cable connector that mates with a first serial cable that transfers the serialized sensor data.
A computer system is designed to process sensor data from multiple sensors, addressing challenges in efficiently handling high-speed, serialized sensor inputs. The system includes a primary analysis coprocessor card that interfaces with a cable connector to receive serialized sensor data via a first serial cable. This coprocessor card is dedicated to analyzing the incoming sensor data, ensuring real-time or near-real-time processing. The system may also include additional coprocessor cards for parallel processing, enhancing throughput and reducing latency. The primary coprocessor card may further communicate with a host processor to offload data processing tasks, improving overall system efficiency. The serialized sensor data is transmitted through the first serial cable, which connects to the primary coprocessor card's cable connector, enabling seamless data transfer. This configuration supports high-speed data acquisition and processing, making it suitable for applications requiring rapid sensor data analysis, such as industrial monitoring, automotive systems, or medical diagnostics. The system's modular design allows for scalability, accommodating varying sensor inputs and processing demands.
4. The computer system of claim 3, further comprising: an acquisition simulator server including a simulation coprocessor card that is configured with a cable connector that mates with a second serial cable connected to the instrument control server for inputting simulated data/frames to the instrument control server without the need for the removable integrated sequencing chip.
This invention relates to a computer system for simulating data acquisition in a sequencing instrument, addressing the need for testing and validation without requiring physical sequencing hardware. The system includes an instrument control server that manages sequencing operations and an acquisition simulator server that generates simulated data frames. The simulator server is equipped with a simulation coprocessor card featuring a cable connector that directly interfaces with the instrument control server via a second serial cable. This setup allows the simulator to input simulated data frames into the control server, bypassing the need for a removable integrated sequencing chip. The system enables testing of sequencing workflows, software, and control logic without physical sequencing hardware, improving efficiency and reducing costs. The simulator can replicate various sequencing scenarios, including error conditions, to validate system performance under different operational states. The direct cable connection ensures low-latency data transfer and synchronization between the simulator and control server, maintaining real-time processing capabilities. This approach streamlines development, debugging, and validation processes in sequencing instrument development.
5. The computer system of claim 2, wherein the first serial cable comprises at least one of: a coaxial cable, a twisted pair copper wire, an optical fiber, and an Ethernet cable.
This invention relates to a computer system designed to enhance data transmission efficiency and reliability. The system addresses the problem of inconsistent or unreliable data transfer between computing devices, particularly in environments where multiple types of serial cables are used. The system includes a first computing device and a second computing device connected via a first serial cable. The first serial cable is configured to transmit data between the devices, and the system ensures compatibility and optimal performance by supporting various cable types, including coaxial cables, twisted pair copper wires, optical fibers, and Ethernet cables. This flexibility allows the system to adapt to different network infrastructures while maintaining high-speed, low-latency data transmission. The system may also include additional components, such as a second serial cable for redundant or parallel data paths, further improving reliability. The invention ensures seamless integration with existing hardware and supports diverse communication protocols, making it suitable for applications in data centers, industrial automation, and telecommunications.
6. The computer system of claim 2, wherein the first primary analysis coprocessor comprises a field programmable coprocessor.
A computer system is designed to enhance processing efficiency by incorporating specialized coprocessors for primary analysis tasks. The system includes a main processor and at least one primary analysis coprocessor, which is a field programmable coprocessor. This coprocessor is configurable to perform specific analysis functions, allowing the main processor to offload computationally intensive tasks. The field programmable nature of the coprocessor enables customization for different analysis requirements, improving flexibility and performance. The system may also include additional coprocessors for secondary analysis, further optimizing workload distribution. By integrating these specialized coprocessors, the system achieves faster processing times and reduced load on the main processor, addressing the need for efficient data analysis in high-performance computing environments. The field programmable coprocessor can be reprogrammed to adapt to evolving analysis needs, ensuring long-term relevance and scalability. This approach is particularly useful in applications requiring real-time data processing, such as scientific simulations, financial modeling, or machine learning tasks.
7. The computer system of claim 6, wherein the instructions for using the first primary analysis coprocessor to transpose instruct the field programmable coprocessor to transpose the frame-by-frame intensity values to create the corresponding plurality of reaction cell chunks, while the plurality of second processors perform the raw base calling.
This invention relates to a computer system for processing sequencing data, specifically optimizing parallel processing of frame-by-frame intensity values from sequencing reactions. The system addresses the challenge of efficiently handling large datasets generated by sequencing instruments, where raw intensity data must be processed in parallel to accelerate base calling while maintaining data integrity. The computer system includes a field-programmable coprocessor configured to transpose frame-by-frame intensity values into reaction cell chunks, enabling parallel processing. While the coprocessor performs the transposition, a plurality of secondary processors execute raw base calling on the original intensity values. This parallelization ensures that the transposition step does not bottleneck the overall workflow. The system further includes a primary analysis coprocessor dedicated to transposing data, allowing the secondary processors to focus solely on base calling without additional computational overhead. The architecture leverages hardware acceleration to improve throughput and reduce latency in sequencing data analysis. The invention improves upon prior systems by decoupling data transformation from base calling, enabling concurrent operations that maximize processor utilization. This approach is particularly beneficial in high-throughput sequencing applications where real-time or near-real-time data processing is required. The system ensures that the transposition of intensity values does not delay the critical path of base calling, thereby enhancing overall efficiency.
8. The computer system of claim 1, wherein the corresponding plurality of reaction cell chunks each represent movie data of the intensity values of a set of n pixels of the image sensor that are assigned to detect the intensity values emitted by the corresponding reaction cell, wherein n is at least one pixel, at least two pixels, at least three pixels, or at least four pixels.
This invention relates to a computer system for processing image data from a reaction cell array, where each reaction cell emits light with intensity values detected by an image sensor. The system divides the image sensor data into chunks, each corresponding to a reaction cell, where each chunk contains intensity values from a set of n pixels assigned to detect the emitted light. The number of pixels (n) per reaction cell can be one, two, three, or four, allowing flexibility in the resolution of the detected data. The system processes these chunks to analyze the reaction cells, improving accuracy in detecting and measuring light intensity variations. This approach enhances the precision of biochemical or biological assays performed in the reaction cells, where light intensity correlates with reaction outcomes. The invention addresses challenges in accurately capturing and interpreting low-light or high-resolution reaction data, ensuring reliable measurement of reaction dynamics. The system's adaptability in pixel allocation per reaction cell optimizes data resolution based on the specific requirements of the assay or imaging conditions.
9. The computer system of claim 8, wherein each of the reaction cells have at least two pixels assigned to detect the intensity values emitted by the corresponding reaction cell.
The invention relates to a computer system for analyzing biological or chemical reactions in a multi-well plate, where each well (reaction cell) contains samples undergoing reactions. The system addresses the challenge of accurately detecting and quantifying reaction intensities, particularly in high-throughput screening applications where precision is critical. Traditional systems often use a single pixel per well, which can lead to inaccuracies due to uneven lighting, sample positioning, or optical noise. The system includes a detection mechanism with at least two pixels assigned to each reaction cell to measure emitted intensity values. These pixels capture redundant data, allowing the system to cross-validate readings and improve accuracy. The system may also include a calibration module to adjust for variations in pixel sensitivity or environmental factors. Additionally, the system may process the intensity values to generate reaction kinetics data, such as reaction rates or endpoint measurements, which are useful for drug discovery or biochemical assays. The use of multiple pixels per well enhances reliability by reducing errors from single-point measurements, making the system suitable for automated laboratory workflows. The invention may also include data normalization and noise filtering to further refine the results.
10. The computer system of claim 8, wherein the intensity values of the pixels for each of the corresponding plurality of reaction cell chunks are stored in contiguous memory locations.
A computer system is designed to process and analyze data from a plurality of reaction cells, such as those used in biological or chemical assays. The system addresses the challenge of efficiently storing and accessing pixel intensity values from these cells, which are often divided into smaller chunks for parallel processing. The invention ensures that the intensity values of pixels for each reaction cell chunk are stored in contiguous memory locations. This contiguous storage arrangement improves data access speed and reduces memory fragmentation, enhancing overall system performance. The system may include a memory controller that manages the storage of pixel intensity values, ensuring that each chunk's data is stored sequentially in memory. Additionally, the system may use a processing unit to analyze the stored intensity values, such as detecting reactions or measuring signal changes within the reaction cells. The contiguous storage method is particularly useful in high-throughput applications where rapid data retrieval and processing are critical. By optimizing memory access patterns, the system enables faster analysis and more efficient use of computational resources.
11. The computer system of claim 8, wherein the first predetermined time window comprises 5-50 seconds, resulting in reaction cell chunks that are approximately 5-50 seconds in length.
This invention relates to a computer system for processing reaction cell data, specifically optimizing the segmentation of reaction cell data into chunks for analysis. The system addresses the challenge of efficiently dividing reaction cell data into manageable segments while preserving meaningful temporal relationships within the data. The system includes a processor and memory storing instructions that, when executed, cause the processor to segment reaction cell data into chunks based on a first predetermined time window. The first time window is set to a duration between 5 and 50 seconds, resulting in reaction cell chunks that are approximately 5 to 50 seconds in length. This segmentation allows for balanced processing, ensuring that each chunk is neither too short to lose contextual information nor too long to become unwieldy for analysis. The system may further include additional processing steps, such as analyzing the segmented chunks to detect specific events or patterns within the reaction cell data. The invention is particularly useful in applications requiring real-time or near-real-time analysis of time-series data, such as chemical reactions, biological processes, or industrial monitoring systems. By optimizing the chunk duration, the system improves computational efficiency and accuracy in data interpretation.
12. The computer system of claim 8, wherein the second predetermined time window comprises 120-160 seconds, resulting in super reaction cell chunks that are approximately 120-160 seconds in length.
This invention relates to a computer system for processing and analyzing data, specifically focusing on segmenting data into reaction cell chunks for improved analysis. The system addresses the challenge of efficiently dividing large datasets into manageable segments while preserving meaningful temporal relationships within the data. The invention includes a method for generating super reaction cell chunks by applying a second predetermined time window of 120-160 seconds to the data. This time window ensures that each resulting super reaction cell chunk is approximately 120-160 seconds in length, allowing for more precise and contextually relevant data analysis. The system first processes the data to create initial reaction cell chunks, which are then further divided or combined into the super reaction cell chunks based on the specified time window. This approach enhances the granularity and accuracy of data analysis by maintaining temporal coherence within each segment. The invention is particularly useful in applications requiring detailed temporal segmentation, such as real-time monitoring, event detection, or time-series data processing. By standardizing the chunk length within the 120-160 second range, the system ensures consistency and reliability in subsequent analytical tasks.
14. The computer system of claim 1, wherein the plurality of logical cores includes C logical cores, and each of the logical cores utilizes a SIMD register having N slots, wherein each slot processes an independent sequencing reaction for a respective reaction cell in the plurality of reaction cells, such that a total number of independent reactions E processed simultaneously for the C multiple cores is: E=C×N.
This invention relates to a computer system for processing sequencing reactions in parallel using multiple logical cores and SIMD (Single Instruction, Multiple Data) registers. The system addresses the challenge of efficiently handling large-scale sequencing data by leveraging parallel processing to accelerate reaction analysis. The computer system includes a plurality of logical cores, each equipped with a SIMD register containing N slots. Each slot in the SIMD register processes an independent sequencing reaction for a corresponding reaction cell. By utilizing C logical cores, the system can simultaneously process a total of E independent reactions, where E is the product of the number of cores (C) and the number of slots per core (N). This parallel processing architecture enhances throughput and efficiency in sequencing data analysis, enabling faster and more scalable processing of genomic information. The system is designed to optimize resource utilization by distributing sequencing reactions across multiple cores and SIMD slots, reducing processing time and improving overall performance. The invention is particularly useful in high-throughput sequencing applications where rapid and accurate data processing is critical.
15. The computer system of claim 1, wherein a second processor in the plurality of second processors supports SIMD instructions.
The invention relates to a computer system designed to enhance parallel processing capabilities. The system includes a primary processor and multiple secondary processors, each capable of executing tasks independently. At least one of these secondary processors supports Single Instruction, Multiple Data (SIMD) instructions, enabling it to perform the same operation on multiple data points simultaneously. This feature improves computational efficiency, particularly for tasks involving large datasets or repetitive operations. The system is configured to distribute workloads across the secondary processors, optimizing performance by leveraging the SIMD capabilities where applicable. The primary processor manages task allocation and coordination, ensuring efficient utilization of the secondary processors. This architecture is particularly useful in applications requiring high-throughput processing, such as scientific computing, data analytics, and real-time signal processing. The inclusion of SIMD support in at least one secondary processor allows the system to handle complex computations more efficiently, reducing processing time and energy consumption. The overall design aims to balance workload distribution and processing speed, making it suitable for both general-purpose and specialized computing environments.
16. The computer system of claim 1, wherein a second processor in the plurality of second processors supports SIMD instructions to convert, in each logical core in the plurality of logical cores, in parallel, the pixel intensity values into base-by-base sequence data, and wherein the SIMD instructions are part of an AVX instruction set.
This invention relates to a computer system designed for parallel processing of pixel intensity values into base-by-base sequence data, particularly in genomic or bioinformatics applications. The system addresses the computational challenge of efficiently converting large datasets of pixel intensity values, often generated by sequencing instruments, into usable sequence data. Traditional methods struggle with the high volume and parallelism required for real-time or near-real-time processing. The system includes a plurality of second processors, each supporting SIMD (Single Instruction, Multiple Data) instructions to process pixel intensity values in parallel across multiple logical cores. Specifically, the SIMD instructions are part of the AVX (Advanced Vector Extensions) instruction set, which enhances throughput by performing the same operation on multiple data points simultaneously. This parallel processing significantly accelerates the conversion of pixel intensity values into base-by-base sequence data, improving efficiency and reducing latency. The system leverages the AVX instruction set's capabilities to handle large datasets efficiently, making it suitable for high-throughput sequencing applications. The parallel execution across logical cores ensures that the conversion process is both fast and scalable, addressing the need for real-time data processing in genomic analysis.
17. The computer system of claim 1, wherein a second processor in the plurality of second processors supports SIMD instructions to convert, in each logical core in the plurality of logical cores, in parallel, the pixel intensity values into base-by-base sequence data, and wherein the SIMD instructions are part of a VIS, MMX, SSE, or Altivec instruction set.
This invention relates to a computer system designed for parallel processing of pixel intensity values into base-by-base sequence data, addressing the need for efficient data conversion in high-performance computing environments. The system includes a plurality of second processors, each capable of executing SIMD (Single Instruction, Multiple Data) instructions to process pixel intensity values in parallel across multiple logical cores. The SIMD instructions belong to instruction sets such as VIS, MMX, SSE, or Altivec, which enable simultaneous operations on multiple data elements, significantly improving processing speed and efficiency. By leveraging these instruction sets, the system converts pixel intensity values into base-by-base sequence data in parallel, enhancing throughput and reducing computational overhead. The use of SIMD instructions allows the system to handle large datasets efficiently, making it suitable for applications requiring high-speed data conversion, such as image processing, bioinformatics, or scientific computing. The parallel processing capability ensures that the conversion is performed across all logical cores simultaneously, optimizing resource utilization and performance. This approach minimizes latency and maximizes processing efficiency, addressing the challenge of handling large-scale data conversion tasks in real-time or near-real-time scenarios.
18. The computer system of claim 1, wherein the primary analysis coprocessor card and the first primary analysis coprocessor are functionally connected to a primary analysis coprocessor printed circuit board by a plurality of bus connectors.
A computer system is designed to enhance data processing efficiency by incorporating specialized coprocessor cards for parallel analysis tasks. The system includes a primary analysis coprocessor card equipped with at least one primary analysis coprocessor, which is dedicated to executing specific computational tasks. This coprocessor card is functionally connected to a primary analysis coprocessor printed circuit board through multiple bus connectors. These connectors facilitate high-speed data transfer and communication between the coprocessor card and the main system, enabling efficient parallel processing. The primary analysis coprocessor is optimized to handle complex analytical workloads, reducing the burden on the central processing unit (CPU) and improving overall system performance. The use of multiple bus connectors ensures robust and scalable connectivity, allowing for future expansion and integration of additional coprocessor cards. This architecture is particularly beneficial in high-performance computing environments where rapid data analysis and processing are critical, such as scientific simulations, financial modeling, and real-time data analytics. The system's modular design allows for easy upgrades and maintenance, ensuring long-term adaptability to evolving computational demands.
19. The computer system of claim 1, wherein the instructions for directly and continually inputting the stream of serialized sensor data into the primary analysis coprocessor card directly and continually input the stream of serialized sensor data into the primary analysis coprocessor card at a rate of at least 450 megabytes per second.
The invention relates to high-speed data processing systems for handling serialized sensor data, particularly in applications requiring real-time analysis. The system includes a primary analysis coprocessor card designed to receive and process a continuous stream of serialized sensor data at high throughput rates. The coprocessor card is optimized to handle data input directly and without interruption, ensuring minimal latency and maximum efficiency in data analysis. The system is configured to input the sensor data stream at a rate of at least 450 megabytes per second, enabling rapid processing for applications such as industrial monitoring, autonomous systems, or scientific research where real-time data analysis is critical. The coprocessor card may include specialized hardware or firmware to manage the high-speed data flow, ensuring that the data is processed as it arrives without bottlenecks. This high-throughput capability allows the system to support multiple high-resolution sensors or complex analytical tasks simultaneously, improving overall system performance and responsiveness. The invention addresses the need for efficient, real-time data processing in environments where large volumes of sensor data must be analyzed continuously.
20. The computer system of claim 1, wherein the machine-readable medium further encodes programming instructions that use the first primary analysis coprocessor to perform dark frame correction, with a dark frame acquired from the image sensor in the absence of light, and gain correction on the frame-by-frame intensity values of the formatted stream of serialized sensor data prior to forming the corresponding plurality of reaction cell chunks.
This invention relates to a computer system for processing image sensor data, specifically addressing the challenges of noise and intensity variation in sensor outputs. The system includes a primary analysis coprocessor that performs dark frame correction and gain correction on raw sensor data before further processing. Dark frame correction involves subtracting a reference dark frame, captured by the image sensor in the absence of light, from each frame of the serialized sensor data to remove fixed-pattern noise. Gain correction adjusts the intensity values of each frame to compensate for variations in sensor sensitivity. These corrections are applied to the formatted stream of serialized sensor data before it is divided into reaction cell chunks for subsequent analysis. The system ensures improved data accuracy by mitigating noise and intensity inconsistencies at an early stage of processing, enhancing the reliability of downstream analytical operations. The primary analysis coprocessor handles these corrections efficiently, optimizing the preprocessing pipeline for high-throughput applications.
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May 5, 2016
May 14, 2024
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