A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells, each capable of storing multi-bit data corresponding to plural program states and an erased state. The control circuit performs at least two partial program operations for programming the multi-bit data in at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation to increase a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plural program states and a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The memory device according to claim 2, wherein the control circuit is further configured to perform a second verification operation for determining whether the at least two non-volatile memory cells have threshold voltages corresponding to the second program state and the third program state, respectively, after applying the first program pulse and the second program pulse, respectively.
5. The memory device according to claim 4, wherein the control circuit is further configured to apply program pulses to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell, when determining that the first non-volatile memory cell fails to have a threshold voltage corresponding to the second program state as a result of the second verification operation.
6. The memory device according to claim 4, wherein the control circuit is further configured to apply program pulses to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell, when determining that the second non-volatile memory cell fails to have a threshold voltage corresponding to the third program state as a result of the second verification operation.
12. The method according to claim 10, further comprising performing a second verification operation for the second program state and the third program state after applying the first program pulse and the second program pulse.
13. The method according to claim 12, further comprising applying program pulses to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell, when determining that the first non-volatile memory cell fails to have a threshold voltage corresponding to the second program state based on a result of the second verification operation.
14. The method according to claim 12, further comprising applying program pulses to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell, when determining that the second non-volatile memory cell fails to have a threshold voltage corresponding to the third program state based on a result of the second verification operation.
17. The memory system according to claim 16, wherein the memory device is further configured to transmit a completion signal to the controller when a program operation regarding the multi-bit data is completed.
19. The memory system according to claim 16, wherein the memory device is further configured to perform a second verification operation for the second program state and the third program state after applying the first program pulse and the second program pulse.
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February 16, 2022
May 21, 2024
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