A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein a side surface of the second silicon portion vertically aligns with a side surface of the first sidewall spacer.
3. The method of claim 1, wherein a side surface of the third silicon portion vertically aligns with a side surface of the second sidewall spacer.
6. The method of claim 1, wherein a top surface of the first sidewall spacer is exposed.
7. The method of claim 1, wherein the phase change material layer comprises a single layer or a multilayer that includes a phase change material.
8. The method of claim 1, wherein a doping concentration of the first doped region ranges from 1016 atom/cm2 to 1020 atom/cm2.
9. The method of claim 1, wherein a doping concentration of the second doped region ranges from 1016 atom/cm2 to 1020 atom/cm2.
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May 11, 2022
May 28, 2024
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