Patentable/Patents/US-12001847
US-12001847

Processor implementing parallel in-order execution during load misses

PublishedJune 4, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A processor may include an instruction pipeline that executes program instructions in-order according to a program order. During operation, the instruction pipeline may detect that data is missing for a first instruction. In response, the instruction pipeline may send a request to load the missing data for the first instruction. However, the instruction pipeline may not necessarily stall operation to wait for the missing data to be loaded. Instead, the instruction pipeline may continue executing instructions subsequent to the first instruction. During the continued execution, the instruction pipeline may detect that data is missing for a second instruction, and send a request to load the missing data for the second instruction. The instruction pipeline may continue such operation until it determines that a condition occurs that prevents the continued execution. When the condition occurs, the instruction pipeline may stop the continued execution, and then re-execute the first instruction.

Patent Claims
5 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The processor of claim 1, wherein the instruction pipeline is configured to determine that the condition occurs based on a determination that the missing data of the first instruction is required by another instruction of the sequence of instructions.

5

5. The processor of claim 1, wherein responsive to a determination that the condition occurs, the instruction pipeline is configured to re-execute the sequence of instructions using the missing data loaded for the first instruction.

10

10. The device of claim 9, wherein the instruction pipeline is configured to determine that the condition occurs based on a determination that the missing data of the first program instruction is required by another program instruction of the sequence of instructions.

13

13. The device of claim 9, wherein responsive to a determination that the condition occurs, the instruction pipeline is configured to re-execute the sequence of instructions using the missing data loaded for the first program instruction.

17

17. The method of claim 16, wherein determining that the condition occurs comprises determining that the missing data of the first instruction is required by another instruction of the sequence of instructions.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

August 30, 2022

Publication Date

June 4, 2024

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Cite as: Patentable. “Processor implementing parallel in-order execution during load misses” (US-12001847). https://patentable.app/patents/US-12001847

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