In one embodiment, a processor includes: a graphics processor to execute a workload; and a power controller coupled to the graphics processor. The power controller may include a voltage ramp circuit to receive a request for the graphics processor to operate at a first performance state having a first operating voltage and a first operating frequency and cause an output voltage of a voltage regulator to increase to the first operating voltage. The voltage ramp circuit may be configured to enable the graphics processor to execute the workload at an interim performance state having an interim operating voltage and an interim operating frequency when the output voltage reaches a minimum operating voltage. Other embodiments are described and claimed.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The processor of claim 1, wherein the second operating voltage comprises an interim operating voltage less than the first operating voltage.
3. The processor of claim 1, wherein the plurality of clock generators comprises at least one phase locked loop to generate the clock signal.
4. The processor of claim 3, wherein the second performance state has an interim operating frequency less than the first operating frequency of the first performance state.
5. The processor of claim 4, wherein the at least one phase locked loop is to dynamically drift output of the clock signal from the interim operating frequency to another interim operating frequency during the execution of the workload.
6. The processor of claim 1, further comprising a table to store a plurality of entries, each of the plurality of entries to associate a voltage ramp value with a time duration.
7. The processor of claim 6, wherein the GPU is to execute the workload at the second performance state after the time duration of an entry of the table associated with the second operating voltage.
8. The processor of claim 1, wherein the power controller comprises a microcontroller.
9. The processor of claim 1, wherein the power controller is to cause a first graphics engine to operate at a higher performance state based on availability of a power budget.
10. The processor of claim 1, further comprising at least one special function unit.
11. The processor of claim 1, wherein the voltage regulator comprises an integrated voltage regulator.
12. The processor of claim 1, wherein the GPU is to couple to a central processing unit (CPU) via a high speed interconnect.
13. The processor of claim 12, further comprising a shared cache memory, wherein a first portion of the shared cache memory is to be allocated to the CPU and second portion of the shared cache memory is to be allocated to the GPU.
16. The method of claim 15, further comprising causing the graphics processing unit to execute the workload at the different performance state when the output voltage reaches a minimum operating voltage less than the first operating voltage.
18. The non-transitory storage medium of claim 17, wherein the instructions further cause the power controller to allocate a power budget between the graphics processing unit and a central processing unit coupled to the graphics processing unit.
19. The non-transitory storage medium of claim 17, wherein the instructions further cause the power controller to cause a first core of the central processing unit to operate at a higher performance state when there is available power budget.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 2, 2021
June 11, 2024
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