A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The method of claim 1, wherein depositing the first conductive hydrogen barrier layer comprises utilizing a first atomic layer deposition process to blanket deposit the first conductive hydrogen barrier layer on the first conductive interconnect and on sidewalls of the etch stop layer to form a conductive hydrogen barrier layer having a lateral portion and substantially vertical portions connected to the lateral portion, and wherein depositing the first conductive hydrogen barrier layer comprises using a second atomic layer deposition process to deposit a material comprising TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO, or METGLAS series of alloys.
4. The method of claim 1, wherein depositing the second dielectric comprises utilizing an atomic layer deposition process to deposit a material comprising a transition metal and oxygen, such as but not limited to AlXOY, HfOX, ZrOX, TaOX, or TiOX.
5. The method of claim 1, wherein depositing the second dielectric comprises utilizing a plurality of processing operations where a first operation comprises utilizing a physical vapor deposition (PVD) process to a material comprising a transition metal and oxygen, such as but not limited to AlxOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN, where the PVD process deposits the second dielectric to a thickness of less than 5 nm, and further wherein the PVD process does not utilize a hydrogen containing precursor.
6. The method of claim 5, further comprises an atomic layer deposition or a chemical vapor deposition process to deposit a material comprising AlXOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN.
7. The method of claim 1, wherein depositing the third dielectric further comprises depositing the third dielectric on a second uppermost surface of the second dielectric and performing a first planarization process to remove the third dielectric from the second uppermost surface, and wherein the first planarization process forms the second uppermost surface and a third uppermost surface of the third dielectric that are substantially co-planar.
8. The method of claim 1, wherein forming first electrode structure further comprises performing a second planarization process to form the first conductive material comprising a substantially planar fourth uppermost surface, and wherein the planar fourth uppermost surface is substantially co-planar with a fifth uppermost surface of the etch stop layer.
9. The method of claim 1, wherein the via electrode is a first via electrode, the memory device is a first memory device, wherein etching the material layer stack further comprises forming a second memory device on a first plane behind the first memory device on a second plane, and wherein the third process further comprises forming a second via electrode on the second memory device, wherein forming the third opening in the fourth dielectric further comprises forming a fifth opening and exposing the second via electrode, and wherein depositing the third conductive hydrogen barrier layer further comprises depositing on the second via electrode.
10. The method of claim 9, wherein depositing the third one or more conductive materials further comprises depositing a liner layer and a conductive fill material on the liner layer.
11. The method of claim 1, wherein after depositing the third one or more conductive materials in the trench opening, a third planarization process is performed, and wherein the third planarization process forms a substantially planar sixth uppermost surface of the contact electrode that is co-planar with a seventh uppermost surface of the metal line.
12. The method of claim 1, wherein the via electrode comprises a first lateral thickness that is less than a second lateral thickness of the memory device, and wherein the third opening comprises a third lateral thickness that is greater than the first lateral thickness.
15. The method of claim 14, wherein performing the planarization comprises forming a vertical thickness of the third dielectric above the second dielectric that is at least equal to a vertical thickness of the contact electrode.
16. The method of claim 14, wherein etching the third dielectric to form the hanging trench further comprises etching to a level that is substantially co-planar with an uppermost surface of the via electrode.
17. The method of claim 15, wherein etching the material layer stack further recesses the etch stop layer to a level below an interface between the memory device and the etch stop layer, and wherein depositing the second dielectric further comprises depositing below the interface.
19. The method of claim 18, wherein depositing the liner layer comprises simultaneously depositing the liner layer in the via opening, in the hanging trench and in the trench opening and on the uppermost surface of the fourth dielectric.
20. The method of claim 18, wherein the via opening in the third dielectric comprises a first lateral width that is between 25-75% of a second lateral width of the hanging trench.
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December 16, 2021
June 11, 2024
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