A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.
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3. The method of claim 1, wherein depositing the first conductive hydrogen barrier layer comprises utilizing a first atomic layer deposition process to blanket deposit the first conductive hydrogen barrier layer on the first conductive interconnect and on sidewalls of the etch stop layer to form a conductive hydrogen barrier layer having a lateral portion and substantially vertical portions connected to the lateral portion, and wherein depositing the first conductive hydrogen barrier layer comprises using a second atomic layer deposition process to deposit a material comprising TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO, or METGLAS series of alloys.
This invention relates to semiconductor manufacturing, specifically to methods for depositing conductive hydrogen barrier layers in integrated circuits to prevent hydrogen-induced degradation of sensitive materials, such as high-k dielectrics. The problem addressed is the diffusion of hydrogen into critical regions of a semiconductor device, which can degrade performance and reliability. The method involves depositing a first conductive hydrogen barrier layer using atomic layer deposition (ALD) to blanket coat a first conductive interconnect and the sidewalls of an etch stop layer. The ALD process forms a barrier layer with a lateral portion over the interconnect and substantially vertical portions connected to the lateral portion, ensuring full coverage. The barrier layer is deposited using a second ALD process and comprises materials such as TiAlN with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti, or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO, or METGLAS series alloys. These materials are selected for their hydrogen diffusion resistance and conductivity, ensuring effective barrier properties while maintaining electrical performance. The method ensures uniform coverage and adhesion, preventing hydrogen diffusion into underlying layers.
4. The method of claim 1, wherein depositing the second dielectric comprises utilizing an atomic layer deposition process to deposit a material comprising a transition metal and oxygen, such as but not limited to AlXOY, HfOX, ZrOX, TaOX, or TiOX.
This invention relates to semiconductor manufacturing, specifically to methods for depositing dielectric materials in integrated circuits. The problem addressed is the need for high-quality, conformal dielectric layers with precise composition control, particularly for advanced semiconductor devices where thin, uniform films are critical. The method involves depositing a second dielectric layer using atomic layer deposition (ALD), a technique that enables atomic-scale control over film thickness and composition. The deposited material is a transition metal oxide, such as AlXOY, HfOX, ZrOX, TaOX, or TiOX, where X and Y represent stoichiometric ratios. ALD ensures uniform coverage on complex 3D structures, which is essential for modern semiconductor devices with high aspect ratio features. The process involves sequential, self-limiting reactions of precursor gases, allowing precise layer-by-layer deposition. This approach improves dielectric film quality by minimizing defects and ensuring consistent electrical properties. The transition metal oxides provide high dielectric constants, making them suitable for gate insulators, capacitors, or passivation layers. The ALD process also allows for doping or alloying to tailor the material's properties further. This method is particularly useful in advanced logic and memory devices where precise control over dielectric properties is required.
5. The method of claim 1, wherein depositing the second dielectric comprises utilizing a plurality of processing operations where a first operation comprises utilizing a physical vapor deposition (PVD) process to a material comprising a transition metal and oxygen, such as but not limited to AlxOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN, where the PVD process deposits the second dielectric to a thickness of less than 5 nm, and further wherein the PVD process does not utilize a hydrogen containing precursor.
This invention relates to semiconductor manufacturing, specifically to methods for depositing thin dielectric layers in integrated circuits. The problem addressed is achieving high-quality, ultra-thin dielectric films without hydrogen contamination, which can degrade device performance. The solution involves depositing a second dielectric layer using a multi-step process where the first step employs physical vapor deposition (PVD) to deposit a transition metal oxide or nitride material. Suitable materials include AlxOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN. The PVD process deposits the dielectric to a thickness of less than 5 nm without using hydrogen-containing precursors, preventing hydrogen-related defects. The method ensures precise control over film thickness and composition, enhancing dielectric properties for advanced semiconductor applications. This approach is particularly useful in forming high-k dielectric layers or barrier layers in transistors, capacitors, or memory devices, where hydrogen contamination must be minimized to maintain electrical reliability. The PVD process provides a clean, hydrogen-free deposition alternative to chemical vapor deposition (CVD) or atomic layer deposition (ALD), improving device yield and performance.
6. The method of claim 5, further comprises an atomic layer deposition or a chemical vapor deposition process to deposit a material comprising AlXOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN.
This invention relates to semiconductor fabrication, specifically to methods for depositing thin films of high-k dielectric or barrier materials on semiconductor substrates. The problem addressed is the need for precise, uniform deposition of advanced materials like AlXOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN, which are critical for modern semiconductor devices but challenging to deposit with conventional techniques. The method involves using atomic layer deposition (ALD) or chemical vapor deposition (CVD) to deposit these materials onto a substrate. ALD is a cyclic process where precursor gases react sequentially to form thin, conformal layers, while CVD involves simultaneous gas-phase reactions to deposit material. The deposited materials are metal oxides or nitrides, which serve as dielectric layers or diffusion barriers in semiconductor devices. These materials improve device performance by reducing leakage current, enhancing thermal stability, and preventing diffusion of impurities. The deposition process ensures high uniformity and precise thickness control, which are essential for nanoscale semiconductor manufacturing. The materials listed are chosen for their high dielectric constants (k-values) or barrier properties, making them suitable for applications in transistors, capacitors, and interconnect structures. The method may be integrated into existing semiconductor fabrication workflows to enhance device reliability and performance.
7. The method of claim 1, wherein depositing the third dielectric further comprises depositing the third dielectric on a second uppermost surface of the second dielectric and performing a first planarization process to remove the third dielectric from the second uppermost surface, and wherein the first planarization process forms the second uppermost surface and a third uppermost surface of the third dielectric that are substantially co-planar.
This invention relates to semiconductor manufacturing, specifically to a method of depositing and planarizing dielectric layers in integrated circuit fabrication. The problem addressed is achieving precise planarization of multiple dielectric layers to ensure uniformity and avoid defects during subsequent processing steps. The method involves depositing a third dielectric layer onto a second dielectric layer, which itself has been deposited over a first dielectric layer. The second dielectric layer is formed by depositing a second dielectric material and performing a planarization process to create a smooth, flat second uppermost surface. The third dielectric layer is then deposited onto this second uppermost surface. A first planarization process is applied to remove excess third dielectric material, resulting in a second uppermost surface of the second dielectric and a third uppermost surface of the third dielectric that are substantially co-planar. This ensures that the surfaces of the stacked dielectric layers are level, which is critical for accurate patterning and deposition in later fabrication steps. The planarization process may include chemical-mechanical polishing (CMP) or other techniques to achieve the desired flatness. The method ensures that the dielectric layers are uniformly deposited and planarized, preventing issues such as uneven etching or deposition in subsequent processes.
8. The method of claim 1, wherein forming first electrode structure further comprises performing a second planarization process to form the first conductive material comprising a substantially planar fourth uppermost surface, and wherein the planar fourth uppermost surface is substantially co-planar with a fifth uppermost surface of the etch stop layer.
This invention relates to semiconductor manufacturing, specifically to methods for forming conductive structures with precise planarization. The problem addressed is achieving a highly planar conductive surface that is co-planar with an adjacent etch stop layer, which is critical for subsequent processing steps in integrated circuit fabrication. The method involves forming a first electrode structure by depositing a first conductive material over a substrate. A second planarization process, such as chemical-mechanical polishing (CMP), is then performed to create a substantially planar fourth uppermost surface on the first conductive material. This planarization ensures that the fourth uppermost surface is co-planar with a fifth uppermost surface of an underlying etch stop layer. The etch stop layer serves as a barrier during etching processes, preventing over-etching into underlying layers. By aligning the planar surfaces of the conductive material and the etch stop layer, the method ensures precise control over subsequent etching and deposition steps, improving device uniformity and reliability. This technique is particularly useful in advanced semiconductor nodes where tight dimensional tolerances are required.
9. The method of claim 1, wherein the via electrode is a first via electrode, the memory device is a first memory device, wherein etching the material layer stack further comprises forming a second memory device on a first plane behind the first memory device on a second plane, and wherein the third process further comprises forming a second via electrode on the second memory device, wherein forming the third opening in the fourth dielectric further comprises forming a fifth opening and exposing the second via electrode, and wherein depositing the third conductive hydrogen barrier layer further comprises depositing on the second via electrode.
This invention relates to semiconductor memory devices, specifically to a method of fabricating a three-dimensional memory structure with multiple memory devices and via electrodes. The problem addressed is the need for efficient electrical interconnection between vertically stacked memory devices while preventing hydrogen diffusion that can degrade device performance. The method involves forming a material layer stack containing multiple memory devices arranged on different planes. A first memory device is formed on a first plane, and a second memory device is formed on a second plane behind the first memory device. Via electrodes are used to electrically connect these memory devices. A first via electrode is formed on the first memory device, and a second via electrode is formed on the second memory device. The process includes etching the material layer stack to create openings that expose these via electrodes. A conductive hydrogen barrier layer is deposited on the via electrodes to prevent hydrogen diffusion, which could otherwise degrade the memory devices. The barrier layer is formed by depositing a conductive material into openings that expose the via electrodes, ensuring reliable electrical connections while maintaining device integrity. This approach enables high-density three-dimensional memory structures with improved reliability and performance.
10. The method of claim 9, wherein depositing the third one or more conductive materials further comprises depositing a liner layer and a conductive fill material on the liner layer.
This invention relates to semiconductor manufacturing, specifically to methods for forming conductive interconnect structures in integrated circuits. The problem addressed is improving the reliability and performance of conductive vias and trenches by optimizing the deposition of conductive materials. The method involves depositing a liner layer followed by a conductive fill material within a via or trench structure. The liner layer, typically a barrier or adhesion layer, prevents diffusion of the conductive fill material into surrounding dielectric materials, ensuring long-term reliability. The conductive fill material, such as copper or tungsten, fills the remaining volume of the via or trench to form an electrically conductive path. The liner layer may be deposited using techniques like physical vapor deposition (PVD) or atomic layer deposition (ALD), while the conductive fill material may be deposited via electroplating, chemical vapor deposition (CVD), or other suitable methods. This sequential deposition ensures proper adhesion, minimizes voids, and enhances electrical conductivity. The method is particularly useful in advanced semiconductor nodes where feature sizes are small, and material diffusion control is critical. By using a liner layer before the conductive fill, the invention improves interconnect reliability, reduces resistance, and prevents electromigration, which are common issues in high-density integrated circuits. The technique is applicable to various semiconductor fabrication processes, including front-end and back-end-of-line (BEOL) interconnect formation.
11. The method of claim 1, wherein after depositing the third one or more conductive materials in the trench opening, a third planarization process is performed, and wherein the third planarization process forms a substantially planar sixth uppermost surface of the contact electrode that is co-planar with a seventh uppermost surface of the metal line.
This invention relates to semiconductor manufacturing, specifically to a method for forming a contact electrode in a trench opening that is co-planar with an adjacent metal line. The problem addressed is achieving precise planarization of conductive materials in a trench to ensure alignment and electrical connectivity with overlying structures while maintaining a flat surface for subsequent processing. The method involves depositing a third set of conductive materials into a trench opening, followed by a third planarization process. This planarization step creates a substantially flat upper surface of the contact electrode that is co-planar with the upper surface of a nearby metal line. The planarization ensures that the contact electrode and metal line are at the same height, preventing misalignment or electrical shorting in later fabrication steps. The process may include multiple deposition and planarization steps for different conductive materials, such as barrier layers, seed layers, and bulk conductive materials, to form a reliable contact structure. The final planarization step ensures uniformity across the wafer surface, which is critical for high-yield semiconductor device manufacturing.
12. The method of claim 1, wherein the via electrode comprises a first lateral thickness that is less than a second lateral thickness of the memory device, and wherein the third opening comprises a third lateral thickness that is greater than the first lateral thickness.
This invention relates to semiconductor memory devices, specifically addressing challenges in forming conductive via electrodes that connect to memory cells. The problem involves ensuring reliable electrical contact between the via electrode and the memory device while accommodating structural constraints. The solution involves a via electrode with a first lateral thickness that is thinner than the second lateral thickness of the memory device it connects to. Additionally, the via electrode is formed within a third opening that has a third lateral thickness greater than the first lateral thickness of the via electrode. This design allows for precise alignment and improved electrical contact while maintaining structural integrity. The via electrode is positioned to interface with the memory device, ensuring efficient signal transmission. The method includes forming the via electrode with controlled dimensions to match the memory device's structural requirements, optimizing performance and reliability. The invention is particularly useful in advanced memory technologies where precise conductive pathways are critical for device functionality.
15. The method of claim 14, wherein performing the planarization comprises forming a vertical thickness of the third dielectric above the second dielectric that is at least equal to a vertical thickness of the contact electrode.
The invention relates to semiconductor manufacturing, specifically to planarization techniques used in forming conductive and dielectric layers. The problem addressed is achieving precise control over the thickness of dielectric layers during planarization to ensure proper electrical insulation and structural integrity in integrated circuits. The method involves planarizing a third dielectric layer deposited over a second dielectric layer and a contact electrode. The planarization process ensures that the vertical thickness of the third dielectric above the second dielectric is at least equal to the vertical thickness of the contact electrode. This prevents electrical shorting between the contact electrode and overlying conductive layers while maintaining uniformity in the dielectric layer. The planarization may involve chemical-mechanical polishing (CMP) or other etching techniques to achieve the desired thickness uniformity. The method ensures reliable insulation and structural stability in semiconductor devices, particularly in advanced nodes where feature sizes are extremely small.
16. The method of claim 14, wherein etching the third dielectric to form the hanging trench further comprises etching to a level that is substantially co-planar with an uppermost surface of the via electrode.
The invention relates to semiconductor fabrication, specifically to methods for forming conductive structures in integrated circuits. The problem addressed is the precise formation of conductive vias and trenches in multilayer dielectric stacks, ensuring proper electrical connectivity while avoiding over-etching or under-etching issues that can degrade device performance. The method involves etching a third dielectric layer to create a hanging trench, which is a recessed trench structure that connects to an underlying via electrode. The etching process is controlled to stop at a level that is substantially co-planar with the uppermost surface of the via electrode. This ensures that the hanging trench is properly aligned and depth-controlled, preventing excessive etching that could damage the via electrode or insufficient etching that could leave residual dielectric material. The via electrode is a conductive structure formed in a lower dielectric layer, providing vertical electrical connectivity between different layers of the integrated circuit. The hanging trench is then filled with a conductive material to form a conductive path that extends from the via electrode to an overlying interconnect layer. This method improves manufacturing yield and reliability by ensuring precise alignment and depth control during the etching process.
17. The method of claim 15, wherein etching the material layer stack further recesses the etch stop layer to a level below an interface between the memory device and the etch stop layer, and wherein depositing the second dielectric further comprises depositing below the interface.
This invention relates to semiconductor manufacturing, specifically to methods for etching and depositing dielectric materials in memory device fabrication. The problem addressed is controlling etch depth and dielectric deposition in structures where precise material layer alignment is critical, particularly at interfaces between memory devices and etch stop layers. The method involves etching a material layer stack that includes an etch stop layer, where the etching process further recesses the etch stop layer below its original interface with an adjacent memory device. This creates a recessed region below the interface. A second dielectric material is then deposited, filling this recessed area and extending below the original interface. The process ensures proper dielectric coverage while maintaining structural integrity at the memory device-etch stop layer boundary. The technique is particularly useful in advanced memory technologies where precise control of etch depth and dielectric deposition is required to prevent defects or performance degradation. By recessing the etch stop layer and depositing dielectric material below the interface, the method improves reliability and electrical isolation in memory devices. The approach may be applied in various memory architectures, including but not limited to flash memory, DRAM, or emerging non-volatile memory technologies.
19. The method of claim 18, wherein depositing the liner layer comprises simultaneously depositing the liner layer in the via opening, in the hanging trench and in the trench opening and on the uppermost surface of the fourth dielectric.
This invention relates to semiconductor fabrication, specifically to a method for depositing a liner layer in a multi-level interconnect structure. The problem addressed is the challenge of uniformly depositing a liner layer in complex via and trench openings while avoiding defects such as voids or poor adhesion. The method involves depositing a liner layer simultaneously in multiple openings, including a via opening, a hanging trench, and a trench opening, as well as on the uppermost surface of a dielectric layer. The liner layer is deposited in a single step to ensure uniform coverage and adhesion across all features. The hanging trench is a recessed trench formed in a lower dielectric layer, while the via opening and trench opening are formed in an upper dielectric layer. The liner layer is deposited using a conformal deposition technique, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), to ensure consistent thickness and coverage. This approach improves reliability by reducing defects and enhancing electrical connectivity in advanced semiconductor devices. The method is particularly useful in multi-level interconnect structures where precise liner deposition is critical for device performance.
20. The method of claim 18, wherein the via opening in the third dielectric comprises a first lateral width that is between 25-75% of a second lateral width of the hanging trench.
The invention relates to semiconductor manufacturing, specifically to the formation of via openings and trenches in dielectric layers to improve electrical connectivity and structural integrity in integrated circuits. The problem addressed is optimizing the dimensions of via openings relative to adjacent trenches to enhance manufacturing yield and device performance. The method involves forming a via opening in a third dielectric layer, where the via opening has a first lateral width that is between 25-75% of a second lateral width of a hanging trench. The hanging trench is a recessed feature in an underlying dielectric layer, typically used for isolation or structural support. The via opening is aligned with the hanging trench but has a narrower width to ensure precise alignment and reduce misalignment risks during etching or deposition processes. This dimensional relationship improves the reliability of electrical connections between conductive layers while maintaining structural stability. The method may also include forming conductive material within the via opening to establish electrical contact between stacked semiconductor layers. The controlled width ratio ensures consistent manufacturing outcomes, minimizing defects such as voids or short circuits. The technique is particularly useful in advanced node semiconductor fabrication where feature sizes are critically small.
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December 16, 2021
June 11, 2024
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