A memory system includes a first memory die including multiple planes each including a plurality of memory cells and a controller configured to perform data communication with the first memory die through a first channel, and transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to the first memory die. After transferring an erase command to a plane among the multiple planes, the controller transfers a read command, a program command, or a check command to another plane among the multiple planes while the first memory die performs an erase operation corresponding to the erase command in the plane.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The memory system of claim 3, wherein the data buffer and distributor comprise multiple buffers, each buffer corresponding to each of the multiple planes.
5. The memory system of claim 3, wherein the control circuit is capable of changing or adjusting an execution sequence of commands input from the controller, to prevent another erase operation from being performed in other planes among the multiple planes while the first memory die performs the erase operation corresponding to the erase command in the plane.
7. The memory system of claim 6, wherein the second memory die is configured to, while performing an erase operation in a plane of the multiple second planes based on other commands input from the controller, perform a read operation, a program operation, or a check operation in other planes of the multiple second planes based on the other commands.
9. The memory system of claim 8, wherein the data buffer and distributor comprise multiple buffers each corresponding to a plane of the multiple first planes.
10. The memory system of claim 8, wherein the control circuit is capable of changing or adjusting an execution sequence of the commands input from the controller, to prevent another erase operation from being performed in other planes among the multiple first planes while the first memory die performs the erase operation corresponding to the erase command in the plane among the multiple first planes.
12. The memory device of claim 11, wherein the plurality of non-volatile memory cells and the control circuit are implemented in a single semiconductor chip.
13. The memory device of claim 11, wherein the plurality of non-volatile memory cells and the control circuit are implemented in different semiconductor chips.
14. The memory device of claim 11, wherein the multiple data buffers and the multiple command buffers have a first-in, first-out (FIFO) data structure.
15. The memory device of claim 11, wherein the control circuit is configured to, when transmitting or receiving a data buffer among the multiple data buffers, obstruct data transmission/reception in other data buffers among the multiple data buffers.
16. The memory device of claim 11, wherein the control circuit is configured to change or adjust the execution sequence according to whether data transmission/reception is required for operations performed in the multiple groups.
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October 21, 2021
June 18, 2024
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