Microelectronic devices including memory cell structures, and related methods and electronic systems

2. The microelectronic device of claim 1, wherein the central portion of the at least one memory cell structure exhibits a minimum width proximate the digit line contact.

3. The microelectronic device of claim 1, wherein the first end portion of the at least one memory cell structure comprises at least one arcuate surface and at least one substantially linear surface.

4. The microelectronic device of claim 1, wherein a distal end of the first end portion of the at least one memory cell structure exhibits an arcuate surface.

5. The microelectronic device of claim 1, wherein the first end portion of the at least one memory cell structure comprises opposing arcuate surfaces.

6. The microelectronic device of claim 1, wherein the at least one memory cell structure is located between at least two other memory cell structures.

7. The microelectronic device of claim 6, wherein a distance between the at least one memory cell structure and a first of the at least two other memory cells structures is different than a distance between the at least one memory cell structure and a second of the at least two other memory cell structures.

8. The microelectronic device of claim 1, further comprising a first word line between the central portion and the first end portion of the at least one memory cell structure.

9. The microelectronic device of claim 8, further comprising a second word line between the central portion and the second end portion of the at least one memory cell structure.

11. The microelectronic device of claim 1, wherein the first end portion comprises a substantially linear surface substantially parallel to a substantially linear surface of the second end portion.

12. The microelectronic device of claim 1, further comprising a storage node structure in electrical communication with the first storage node contact.

13. The microelectronic device of claim 1, wherein the non-zero angle is within a range between about 20 degrees and about 70 degrees.

14. The microelectronic device of claim 1, wherein the non-zero angle is within a range between about 40 degrees and about 50 degrees.

15. The microelectronic device of claim 1, wherein a size of the first end portion and a size of the second end portion are substantially the same.

16. The microelectronic device of claim 1, wherein the digit line contact of the at least one memory cell structure is horizontally aligned with a storage node contact of a horizontally neighboring memory cell structure.

17. The microelectronic device of claim 1, wherein the first end portion comprises a substantially linear surface distal from the digit line contact.

18. The microelectronic device of claim 1, wherein a substantially linear surface of the first end portion of the at least one memory cell structure is parallel to a substantially linear surface of an additional end portion of a horizontally neighboring additional memory cell structure.

19. The microelectronic device of claim 1, further comprising a digit line vertically overlying the central portion and extending substantially parallel to the longitudinal axis of the central portion.

20. The microelectronic device of claim 19, wherein a width of the digit line in a horizontal direction that is substantially orthogonal to another horizontal direction in which the digit line extends is less than a width of the central portion in the horizontal direction.

21. The microelectronic device of claim 1, wherein the first end portion is in contact with the first storage node contact at a distal end of the first end portion relative to the central portion.

22. The microelectronic device of claim 21, wherein the distal end of the first end portion lies along the longitudinal axis of the first end portion.

23. The microelectronic device of claim 1, wherein the elongated pillars comprise a first semiconductive pillar at the first end portion, the first storage node contact overlapping a first side of the first semiconductive pillar, and the first side of the first semiconductive pillar being a distal side relative to the central portion.

25. The method of claim 24, wherein forming lines of a material comprising at least some nonlinear surfaces comprises forming lines exhibiting a sinusoidal shape.

26. The method of claim 24, wherein forming lines of a material comprising at least some nonlinear surfaces comprises forming lines comprising first portions and second portions, each line comprising first portions comprising arcuate surfaces and a larger dimension than a second portion between neighboring first portions of the line.

27. The method of claim 24, wherein forming a mask over the spacers comprises forming the mask to include trenches extending at an angle with respect to the spacers.

28. The method of claim 27, further comprising removing portions of the spacers through the trenches in the mask.

29. The method of claim 24, wherein forming a mask over the spacers comprises forming the mask to include circular openings.

30. The method of claim 29, further comprising removing portions of the spacers through the circular openings in the mask.

31. The method of claim 24, wherein removing a portion of the spacers through the mask to form isolated structures comprises forming the isolated structures to comprise the central portion comprising the opposing arcuate surfaces.

32. The method of claim 24, wherein removing a portion of the spacers through the mask to form isolated structures comprises forming the isolated structures to comprise the central portion between the first end portion and the second end portion, each of the first end portion and the second end portion individually comprising a terminal portion comprising an arcuate surface.