A semiconductor package includes a semiconductor chip having first and second contact pads that are alternately arranged in a first direction; an insulating film having first openings respectively defining first pad regions of first contact pads, and second openings respectively defining second pad regions of the second contact pads; first and second conductive capping layers on the first and second pad regions, respectively; and an insulating layer on the insulating film, and having first and second contact holes respectively connected to the first and second conductive capping layers. Each of the first and second pad regions includes a bonding region having a first width and a probing region having a second width, greater than the first width, and each of the second pad regions is arranged in a direction that is opposite to each of the plurality of first pad regions.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor package of claim 1, wherein each of the first and second conductive capping layers comprises a third region having a third width and a fourth region having a fourth width, different from the third width, and the first conductive capping layers and the second conductive capping layers are different in shape with respect to the first direction.
3. The semiconductor package of claim 1, wherein each of the plurality of first and second contact pads comprises a square shape or a rectangular shape in a plan view.
4. The semiconductor package of claim 1, wherein the first and second openings are arranged such that the first region and the second region of two adjacent first and second pad regions face each other in the first direction.
5. The semiconductor package of claim 2, wherein the first and second conductive capping layers are arranged such that the third region and the fourth region of two adjacent first and second conductive capping layers face each other in the first direction.
6. The semiconductor package of claim 2, wherein the second width of the second region is greater than the first width of the first region, and the fourth width of the fourth region is greater than the third width of the third region.
7. The semiconductor package of claim 6, wherein the first region overlaps the third region, and the third width is 5 μm to 30 μm larger than the first width.
8. The semiconductor package of claim 6, wherein the second region overlaps the fourth region, and the fourth width is 5 μm to 30 μm larger than the second width.
9. The semiconductor package of claim 1, wherein each of the plurality of first and second contact pads comprises a concave probing mark in the second region.
11. The semiconductor package of claim 10, wherein the plurality of first and second contact holes overlaps the first regions of the first or second pad regions, respectively.
13. The semiconductor package of claim 10, wherein at least one of the insulating film and the insulating layer comprises a photosensitive insulating material.
14. The semiconductor package of claim 1, further comprising an insulating protective film between the active surface of the semiconductor chip and the insulating film.
17. The semiconductor package of claim 16, wherein the redistribution structure has an area that is larger than the area of the semiconductor chip.
18. The semiconductor package of claim 17, further comprising an encapsulant on the redistribution structure and on the semiconductor chip.
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January 27, 2023
July 2, 2024
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