Device scaling has increased the device density of integrated circuits (ICs) and reduced the cost of circuits. Today development of new device structures, use of new materials and implementation of complex process steps are implemented to continue scaling of the semiconductor devices. The added manufacturing steps and complexity have increased cost of ICs directly impacting the implementation of IoT devices that need low cost and high yields to be successful. LEFT-ISD-LTSEE is a device that reduces the cost while improving device performance. LEFT-ISD-LTSEE is suitable for sub 28 nm sizes where random threshold variation due to impact of discrete dopants in and around the channel is reduced by elimination of implants and drives. Also, by having a flat field profile at and around the gate, by use of low temperature epitaxy as source/drain extension, the short channel effects, and the impact of line edge variations of the gate are reduced.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The transistor structure of claim 1 wherein the substrate has doping of a first type and the shallow implanted source and drain and the epitaxial source extension and drain extension all have doping of a second type.
3. The transistor structure of claim 1 wherein the conductive gate electrode is metallic or semiconductor.
4. The transistor structure of claim 1 wherein the epitaxial source and drain extensions are deposited by selective epitaxy.
5. The transistor structure of claim 4 wherein the epitaxial source and drain extensions have a crystal structure that is continuous with that of the substrate.
6. The transistor structure of claim 1 wherein the epitaxial source and the epitaxial drain extensions over laying the substrate including the shallow implanted source and drain have a crystal structure that is continuous with that of the substrate.
7. The transistor structure of claim 1 wherein the protective dielectric that separates the epitaxial source extension and the epitaxial drain extension from the gate is as thick as or thicker than the gate dielectric thickness.
8. The transistor structure of claim 1, wherein a silicide is formed on the surface of the epitaxial source and epitaxial drain extensions over the shallow implanted source and drain for making contact to the shallow implanted source and drain and the source and drain extensions.
9. The transistor structure of claim 1 wherein an electrostatic fields perpendicular to an interface plane between the gate dielectric and the substrate are less than 5×105 volts/cm over more than 50% of an area of the channel under all operating conditions.
10. The transistor structure of claim 1 wherein the substrate having a doping of 1016 to 5×1017 atoms per cm−3.
11. The transistor structure of claim 1 wherein the substrate has a well doping that is retrograde in nature.
12. The transistor structure of claim 1 wherein the substrate comprises a surface layer that is an epitaxial layer deposited over the substrate.
13. The transistor structure of claim 1 in which the substrate comprises silicon over an insulator.
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January 19, 2024
July 9, 2024
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