A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, wherein the at least one fuse comprises at least two fuses.
3. The semiconductor device of claim 2, wherein the at least one fuse comprises at least three fuses.
4. The semiconductor device of claim 1, wherein the first metal layer has a thickness of between about 400 Å and about 1000 Å.
5. The semiconductor device of claim 1, wherein a via within the second metal layer has a thickness of between about 400 Å and about 800 Å.
6. The semiconductor device of claim 1, wherein the second metal lines have a thickness of between about 600 Å and about 1200 Å.
7. The semiconductor device of claim 1, wherein the at least one fuse has a width of between about 200 Å and about 400 Å.
9. The semiconductor device of claim 8, wherein the semiconductor substrate is separated from the first fuse by at least a second metal layer.
10. The semiconductor device of claim 9, wherein the second metal layer has a first plurality of metal lines that are perpendicular to the plurality of gate electrodes.
11. The semiconductor device of claim 10, wherein the semiconductor substrate is further separated from the first fuse by at least a third metal layer.
12. The semiconductor device of claim 11, wherein the third metal layer has a second plurality of metal lines that is parallel to the plurality of gate electrodes.
13. The semiconductor device of claim 8, wherein the first region has a first width of between about 200 μm and about 400 μm and a first length of between about 100 μm and about 300 μm.
14. The semiconductor device of claim 8, wherein the first region is a fuse bit cell area.
16. The semiconductor device of claim 15, further comprising a second layer located between the first layer and the semiconductor substrate, the second layer comprising a second plurality of metal lines.
17. The semiconductor device of claim 16, further comprising a third layer located between the second layer and the semiconductor substrate, the third layer comprising a third plurality of metal lines.
18. The semiconductor device of claim 17, wherein the first plurality of metal lines is electrically connected to the semiconductor substrate through the second plurality of metal lines and the third plurality of metal lines.
19. The semiconductor device of claim 18, wherein the third plurality of metal lines is perpendicular with the plurality of gate electrodes.
20. The semiconductor device of claim 15, further comprising a fourth layer located on an opposite side of the first layer from the semiconductor substrate, the fourth layer comprising a fourth plurality of metal lines.
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November 17, 2020
July 9, 2024
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