A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.
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2. The semiconductor device of claim 1, wherein a ratio of metal to silicon in the first conformal silicide layer is greater than 1.
3. The semiconductor device of claim 1, wherein a ratio of silicon to metal in the second conformal silicide layer is greater than 1.
4. The semiconductor device of claim 1, wherein a total thickness of the first conformal silicide layer and the second conformal silicide layer is at least approximately 20 angstroms.
5. The semiconductor device of claim 1, wherein a thickness of each of the first conformal silicide layer and the second conformal silicide layer is in a range from approximately 5 angstroms to approximately 10 angstroms.
6. The semiconductor device of claim 1, wherein at least one of the first conformal silicide layer or the second conformal silicide layer comprises at least one of nickel silicide, cobalt silicide, titanium silicide, or tantalum silicide.
8. The semiconductor device of claim 1, wherein the metal compound layer is a metal nitride, a metal oxide, or a transparent metal oxide.
9. The semiconductor device of claim 1, wherein the dielectric material around the contact structure is doped with an enhancement element associated with sealing the contact structure.
10. The semiconductor device of claim 1, wherein the semiconductor device is a three-dimensional (3D) gate-all-around (GAA) metal-oxide-semiconductor field-effect transistor (MOSFET).
12. The method of claim 11, further comprising performing a pre-clean in the recess prior to forming the multi-silicide structure in the recess to remove a native oxide from at least the bottom surface of the recess.
13. The method of claim 11, wherein forming the first conformal silicide layer comprises depositing a metal material on the bottom surface of the recess using a chemical vapor deposition (CVD) process.
14. The method of claim 11, wherein forming the second conformal silicide layer comprises growing the second conformal silicide layer on the first conformal silicide layer using a soaking process.
16. The method of claim 15, wherein the capping layer material is etched from the one or more sidewalls of the recess using an atomic layer etching (ALE) process, wherein a set of etch process parameters used for the ALE process was determined using an analysis model configured to determine sets of etch process parameters.
18. The semiconductor device of claim 17, wherein a ratio of metal to silicon in the first conformal silicide layer is greater than 1.
19. The semiconductor device of claim 17, wherein a ratio of silicon to metal in the second conformal silicide layer is greater than 1.
20. The semiconductor device of claim 17, wherein a thickness of each of the first conformal silicide layer and the second conformal silicide layer is in a range from approximately 5 angstroms to approximately 10 angstroms.
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March 18, 2021
July 16, 2024
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