A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The system of claim 1, wherein a part of the program data stored in the predefined memory region is configured to control the command queue.
3. The system of claim 2, comprising a portion of memory configured to store data to be moved to the second memory chip according to the command queue.
5. The system of claim 1, wherein the first memory chip includes a plurality of memory cells of a non-volatile random access memory.
6. The system of claim 5, wherein the non-volatile random access memory is a 3D XPoint memory.
7. The system of claim 1, wherein the first memory chip includes a dynamic random-access memory.
8. The system of claim 1, wherein the first memory chip includes a flash memory.
10. The system of claim 9, wherein a part of the program data stored in the predefined memory region is configured to control a command queue for the programmable engine.
12. The system of claim 11, wherein the first memory chip includes a non-volatile random-access memory (NVRAM).
13. The system of claim 11, further comprising a third memory.
14. The system of claim 13, wherein the third memory comprises a cache for the first memory chip, and wherein the processor is configured to program the programmable engine by writing data in the predefined memory region in the first memory chip via the cache for the first memory chip.
16. The system of claim 15, wherein a cache is coupled between the processor and the first memory chip.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 29, 2021
July 23, 2024
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