The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor structure according to claim 1, wherein each of the first phase change memory structure and the second phase change memory structure comprises: the bottom electrode, a heating structure, a phase change layer, and the top electrode that are sequentially stacked from bottom to top.
3. The semiconductor structure according to claim 2, wherein the bottom electrode of the first phase change memory structure is located in a same layer with the bottom electrode of the second phase change memory structure, the heating structure of the first phase change memory structure is located in a same layer with the heating structure of the second phase change memory structure, the phase change layer of the first phase change memory structure is located in a same layer with the phase change layer of the second phase change memory structure, and the top electrode of the first phase change memory structure is located in a same layer with the top electrode of the second phase change memory structure.
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June 29, 2022
July 23, 2024
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