An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The image sensor pixel defined in claim 2, wherein the charge storage structure comprises a low gain capacitor.
4. The image sensor pixel defined in claim 2, wherein the charge storage structure and the second transistor are coupled along the sampling path.
10. The image sensor pixel defined in claim 1, wherein the voltage-domain sampling circuitry has fewer than four capacitors.
11. The image sensor pixel defined in claim 10, wherein the voltage-domain sampling circuitry comprises an additional source follower transistor that couples each capacitor in the fewer than four capacitors to the pixel output path.
13. The image sensor pixel defined in claim 12, wherein the first capacitor is configured to sample two types of signals.
14. The image sensor pixel defined in claim 13, wherein the two types of signals are a reset level signal and an image level signal.
15. The image sensor pixel defined in claim 12, wherein the voltage-domain sampling circuitry has a first transistor coupling the first capacitor to the path, a second transistor coupling the second capacitor to the path, and a third transistor coupling the third capacitor to the path.
16. The image sensor pixel defined in claim 12, wherein the photosensitive element, the floating diffusion region, and the low gain capacitor are disposed on a first die, and wherein the voltage-domain sampling circuitry is disposed on a second die.
18. The image sensor defined in claim 17, wherein the voltage-domain sampling stage comprises a second capacitor, and the control circuitry is configured to control the image pixel to store a high conversion gain image level signal at the second capacitor, and wherein the voltage-domain sampling stage comprises a third capacitor, and the control circuitry is configured to control the image pixel to store a high conversion gain reset level signal at the third capacitor.
19. The image sensor defined in claim 17, wherein the control circuitry is configured to control the image pixel to store the low conversion gain reset level signal at the capacitor after performing a readout operation on the stored low conversion gain image level signal.
20. The image sensor defined in claim 17, wherein the image sensor is configured to be an image sensor for a vehicle.
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February 3, 2022
July 23, 2024
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