Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.
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2. The method of claim 1, comprising determining not to immediately proceed with conveying the halt indication based on a determination that the expected arrival time of the next synchronization pulse precedes the expected time of completion of propagation of the halt indication to at least one of the plurality of integrated circuit devices.
3. The method of claim 1, comprising determining to immediately proceed with conveying the halt indication based on a determination that the expected time of completion of propagation of the halt indication to each of the plurality of integrated circuit devices precedes the expected arrival time of the next synchronization pulse.
6. The method of claim 4, wherein the halt logic determines not to immediately proceed with conveying the halt indication based on a determination that the expected arrival time of the next synchronization pulse precedes the expected time of completion of propagation of the halt indication.
7. The method of claim 4, wherein the halt logic determines to immediately proceed with conveying the halt indication based on a determination that the expected time of completion of propagation of the halt indication precedes the expected arrival time of the next synchronization pulse.
8. The method of claim 4, comprising determining the expected arrival time of the next synchronization pulse based on an arrival time of a previously-detected synchronization pulse.
11. The method of claim 4, comprising determining to issue the system halt based on a triggering of an interrupt by one of the plurality of integrated circuit devices.
12. The method of claim 4, wherein the halt logic conveys the halt indication to a synchronization signal node to cause the synchronization signal node to suspend transmission of synchronization pulses in the synchronization signal.
13. The method of claim 12, wherein, responsive to a determination to release the system halt, the halt logic conveys a resume indication to the synchronization signal node to cause the synchronization signal node to resume transmission of synchronization pulses in the synchronization signal.
16. The system of claim 14, wherein the halt logic determines not to immediately proceed with conveying the halt indication based on a determination that the expected arrival time of the next synchronization pulse precedes the expected time of completion of propagation of the halt indication.
17. The system of claim 14, wherein the halt logic determines to immediately proceed with conveying the halt indication based on a determination that the expected time of completion of propagation of the halt indication precedes the expected arrival time of the next synchronization pulse.
19. The system of claim 14, wherein the system controller determines to issue the system halt based on a triggering of an interrupt by one of the plurality of integrated circuit devices.
20. The system of claim 14, wherein the plurality of integrated circuit devices are arranged in a star topology.
21. The system of claim 14, wherein the pulse generator is part of one of the plurality of integrated circuit devices.
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June 6, 2022
July 30, 2024
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