Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
6. The apparatus of claim 1, wherein the first transistor is a p-type metal-oxide-semiconductor (PMOS) transistor and the second transistor is a n-type metal-oxide-semiconductor (NMOS) transistor.
14. The method of claim 13, wherein the sixth voltage is a ground voltage associated with a reset operation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 13, 2022
July 30, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.