A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomizing the memory access operation with a randomization logic to access data from a physical memory space based on the logical memory space, the randomization logic providing time varying behavior for accessing the physical memory space.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the randomization logic includes a counter and uses a hash value that changes over time.
3. The method of claim 2, wherein the randomization logic is configured to generate an address for the physical memory space based on a logical address and the hash value.
4. The method of claim 1, wherein the randomization logic is configured to change an arrangement of bits within a data word that is read from or written to the physical memory space, such that a permutation of the bits of the read data word and a permutation of the bits of the written data word are inversed.
5. The method of claim 1, wherein the randomization logic is used in the memory space of a low-density parity check (LDPC) decoder and the LDPC decoder repeats the memory access operation with different memory space randomizations.
7. The decoder of claim 6, wherein the randomization logic includes a counter and uses a hash value that changes over time.
8. The decoder of claim 7, wherein the randomization logic is configured to generate an address for the physical memory space based on a logical address and the hash value.
9. The decoder of claim 6, wherein the randomization logic is configured to change an arrangement of bits within a data word that is read from or written to the physical memory space, such that a permutation of the bits of the read data word and a permutation of the bits of the written data word are inversed.
10. The decoder of claim 6, wherein the randomization logic is used in the memory space of a low-density parity check (LDPC) decoder and the LDPC decoder repeats the memory access operation with different memory space randomizations.
12. The system of claim 11, wherein the randomization logic includes a counter and uses a hash value that changes over time.
13. The system of claim 12, wherein the randomization logic is configured to generate an address for the physical memory space based on a logical address and the hash value.
14. The system of claim 11, wherein the randomization logic is configured to change an arrangement of bits within a data word that is read from or written to the physical memory space, such that a permutation of the bits of the read data word and a permutation of the bits of the written data word are inversed.
15. The decoder of claim 11, wherein the randomization logic is used in the memory space of a low-density parity check (LDPC) decoder and the LDPC decoder repeats the memory access operation with different memory space randomizations.
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September 23, 2021
August 6, 2024
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