Disclosed a display panel comprising: a base substrate and a plurality of sub-pixels located on the base substrate; and each sub-pixel includes: a semiconductor layer located on the base substrate and including a first active layer of an initialization transistor, a second active layer of a reset transistor and a third active layer of a data writing transistor; a first conductive layer located on a side of the semiconductor layer and including a data signal line extending in a first direction; and a second conductive layer located on the base substrate and including a drive gate of a drive transistor; where the drive gate is electrically connected to a first conductive region of the first active layer; and an orthographic projection of the second active layer on the base substrate is located between an orthographic projection of the first active layer and an orthographic projection of the data signal line.
Legal claims defining the scope of protection, as filed with the USPTO.
5. The display panel according to claim 4, wherein the first portion and the second portion are in a grid structure.
6. The display panel according to claim 4, wherein the each of the plurality of sub-pixels further comprises a storage capacitor, the storage capacitor comprises a first electrode in a third conductive layer, which is different from a layer where the first portion and the second portion are located.
7. The display panel according to claim 6, wherein an orthographic projection of the second portion on the base substrate is overlapped with an orthographic projection of the first electrode on the base substrate.
8. The display panel according to claim 4, wherein the each of the plurality of sub-pixels further comprises a storage capacitor, the storage capacitor comprises a second electrode, and an orthographic projection of the second portion of the fixed potential signal line on the base substrate passes through two sides of an orthographic projection of the second electrode on the base substrate.
10. The display panel according to claim 3, wherein the shielding structure is disposed on the same layer as an initialization signal line.
12. The display panel according to claim 11, wherein an orthographic projection of the second conductive connection part is on a side of the first scanning line away from an initialization signal line, a first distance is between the second conductive connection part and the initialization signal line, and the first distance is greater than a line width of the first scanning line.
14. The display panel according to claim 1, further comprising a light emitting control transistor electrically connected to a first electrode of the light emitting device, wherein the first electrode of at least one light emitting device overlaps with data signal lines corresponding to two columns of sub-pixels in a second direction.
16. The display panel according to claim 1, data signal lines corresponding to two columns of sub-pixels are on a middle part of a first electrode of the light emitting device.
17. The display panel according to claim 1, further comprising a pixel defining layer, wherein the pixel defining layer comprises an opening region, and at least one data line of data signal lines corresponding to two columns of sub-pixels is in the opening region.
18. The display panel according to claim 1, wherein a distance between data signal lines corresponding to two columns of sub-pixels in a first electrode region is less than ½ of a size of a first electrode in a second direction.
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July 25, 2023
August 6, 2024
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