Patentable/Patents/US-12061665
US-12061665

Inverse element arithmetic apparatus and memory system

PublishedAugust 13, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

According to one embodiment, in an inverse element arithmetic apparatus, a word unit processing unit, as approximate calculation loop for extended binary GCD process, iterates a first loop in a case where a value of |r−s| is a subtraction threshold or more, and is capable of iterating a second loop instead of the first loop in a case where the value of |r−s| is smaller than the subtraction threshold. In the first loop, values of r, s, a, b, m, and n is updated and an update matrix M is generated or updated. In the second loop, the values of m and n are updated without updating the values of r, s, a, b and the update matrix M. The control unit terminates the loop of the inverse element arithmetic process in a case where a loop number of times of the inverse element arithmetic process reaches a number-of-times threshold.

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Patent Metadata

Filing Date

March 10, 2021

Publication Date

August 13, 2024

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