Disclosed is an integrated circuit (IC) structure that includes a through-metal through-substrate interconnect. The interconnect extends essentially vertically through a device level metallic feature on a frontside of a substrate, extends downward from the device level metallic feature into or completely through the substrate (e.g., to contact a backside metallic feature below), and extends upward from the device level metallic feature through interlayer dielectric (ILD) material (e.g., to contact a BEOL metallic feature above). The device level metallic feature can be, for example, a metallic source/drain region of a transistor, such as a high electron mobility transistor (HEMT) or a metal-insulator-semiconductor high electron mobility transistor (MISHEMT), which is formed on the frontside of the substrate. The backside metallic feature can be a grounded metal layer. The BEOL metallic feature can be a metal wire in one of the BEOL metal levels. Also disclosed is an associated method.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The structure of claim 1, wherein the structure further comprises a metallic film on the first side of the substrate immediately adjacent to the interconnect.
3. The structure of claim 1, wherein the upper portion is wider than the middle portion.
4. The structure of claim 1, further comprising: an insulator layer in the lower portion of the interconnect opening and electrically isolating the interconnect from the substrate.
5. The structure of claim 1, further comprising an additional interconnect, wherein the additional interconnect is physically separated from any adjacent interconnects, is within an additional interconnect opening that extends from the first side of the substrate through the metallic feature and further through the second dielectric layer, and is in direct contact with and electrically connected to the metallic feature.
6. The structure of claim 1, wherein the interconnect further comprises at least one of an adhesive layer and a barrier layer lining sidewalls of the interconnect opening and the conductive fill material filling remaining space within the interconnect opening.
8. The structure of claim 7, further comprising a metallic film on the first side of the multi-layered substrate immediately adjacent to the interconnect.
9. The structure of claim 7, wherein the upper portion is wider than the middle portion.
10. The structure of claim 7, wherein the gate structure comprises a gate conductor layer in the gate opening immediately adjacent to the barrier layer.
13. The structure of claim 7, further comprising: an additional interconnect, wherein the additional interconnect is physically separated from any adjacent interconnects, is within an additional interconnect opening that extends from the first side of the multi-layer substrate through the one metallic source/drain region and further through the second dielectric layer, and includes the conductive fill material extending continuously from the first side of the multi-layered substrate through the second dielectric layer.
14. The structure of claim 7, wherein the metallic source/drain regions include two metallic source/drain regions including: a metallic source region and a metallic drain region, and wherein the metallic source region has a larger surface area than the metallic drain region and is closer to the gate structure than the metallic drain region.
15. The structure of claim 8, wherein the conductive fill material is different from metallic materials of the metallic film and the additional metallic feature.
16. The structure of claim 8, wherein the conductive fill material is tungsten.
18. The structure of claim 17, wherein the conductive fill material is different from metallic materials of the metallic film and the BEOL wire.
19. The structure of claim 17, wherein the at least one interconnect includes multiple interconnects.
20. The structure of claim 18, wherein the BEOL wire extends laterally across and is in contact with all of the multiple interconnects.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 30, 2021
August 13, 2024
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