A memory cell includes a flip-flop circuit that includes a first CMOS inverter circuit including a 1Ath transistor TR1 and a 1Bth transistor TR2 and a second inverter circuit including a 2Ath transistor TR3 and a 2Bth transistor TR4 and two transfer transistors TR5 and TR6. The 1Ath transistor TR1 and the 2Ath transistor TR2 are connected to a common first power supply line, and the 1Bth transistor TR3 and the 2Bth transistor TR4 are connected to a common second power supply line.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The memory cell according to claim 2, wherein the common first drain region-connection portion and the common second drain region-connection portion each include a high concentration impurity region or a conductive material layer formed on the substrate.
5. The memory cell according to claim 4, wherein the common first power supply line and the common second power supply line each include a high concentration impurity region or a conductive material layer formed on the substrate.
7. The memory cell according to claim 6, wherein the common first power supply line, the common second power supply line, the first bit line, and the second bit line extend in a first direction.
8. The memory cell according to claim 1, wherein, where a direction in which the common first power supply line, the common second power supply line, a first bit line, and a second bit line extend is assumed to be a first direction and a direction orthogonal to the first direction is assumed to be a second direction, adjacent memory cells are arranged line symmetrically with respect to a boundary line extending in the first direction, a boundary line extending in the second direction, or boundary lines extending in the first direction and the second direction.
9. The memory cell according to claim 1, wherein the first CMOS inverter circuit and the second CMOS inverter circuit are arranged two times symmetrically with respect to a center axis of the memory cell.
11. The memory cell according to claim 1, wherein an orthogonal projection image of the drain region, the channel formation region, and the source region configuring the 1Ath transistor and the drain region, the channel formation region, and the source region configuring the 1Bth transistor to a virtual plane vertical to a first direction, an orthogonal projection image of the drain region, the channel formation region, and the source region configuring the 2Ath transistor and the drain region, the channel formation region, and the source region configuring the 2Bth transistor to a virtual plane vertical to the first direction, an orthogonal projection image of one source/drain region, the channel formation region, and another source/drain region configuring the first transfer transistor to a virtual plane vertical to the first direction, and an orthogonal projection image of one source/drain region, the channel formation region, and another source/drain region configuring the second transfer transistor to a virtual plane vertical to the first direction do not substantially overlap with each other.
17. The memory cell according to claim 16, wherein the common first drain region-connection portion and the common second drain region-connection portion each include a high concentration impurity region or a conductive material layer formed on the substrate.
19. The memory cell according to claim 18, wherein the common first power supply line and the common second power supply line each include a high concentration impurity region or a conductive material layer formed on the substrate.
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August 13, 2019
August 13, 2024
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