Patentable/Patents/US-12068203
US-12068203

Method for manufacturing semiconductor device structure

PublishedAugust 20, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for manufacturing a semiconductor device structure including a doped region under an isolation feature. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises a first well region with a first conductive type; forming an isolation feature extending from the second surface of the substrate; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region under the isolation feature, wherein the first doped region has a second conductive type different from the first conductive type; and providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled with the first doped region.

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Patent Metadata

Filing Date

October 26, 2021

Publication Date

August 20, 2024

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