A memory device includes a stacked structure including a plurality of memory cells, and first and second flights of steps. The first flights of steps are disposed at an end of the stacked structure along the first direction. The second flights of steps are adjacent to the first flights of steps disposed at the end of the stacked structure along the first direction. The first flights of steps and the second flights of steps comprise first portions and second portions alternately disposed along the first direction. The second portions are wider than the first portions along the second direction.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The memory device of claim 1, wherein the second portions of the first flights of steps are disposed in a staggered configuration with respect to the second portions of the second flights of steps.
4. The memory device of claim 1, wherein the width of the first portions along the second direction is larger than the width of the first portions along the second direction.
5. The memory device of claim 1, wherein the stacked structure comprises an upper conductive line and a lower conductive line, the upper conductive line is stacked on the lower conductive line, and at least one more first portion and second portion are connected at each end of the lower conductive line than a number of connective lines and second portions connected at each end of the upper conductive line.
6. The memory device of claim 1, wherein a length along the first direction of the first portions of the first flights of steps directly connected to the end of the stacked structure is greater than a length along the first direction of the first portions of the second flights of steps directly connected to the end of the stacked structure.
12. The semiconductor device of claim 11, wherein the first contact via and the second contact via are formed at opposite sides of the first gate lines and the second gate lines with respect to the second direction.
13. The semiconductor device of claim 11, wherein the third contact via is formed on a same side of the first gate lines as the first contact via, and the fourth contact via is formed at a same side of the second gate lines as the second contact via.
14. The semiconductor device of claim 11, wherein the third contact via is formed on a same side of the first gate lines as the second contact via, and the fourth contact via is formed at a same side of the second gate lines as the first contact via.
16. The method of claim 15, wherein the second portions of the first flights of steps are disposed in a staggered configuration with respect to the second portions of the second flights of steps.
18. The method of claim 15, wherein the width of the first portions along the second direction is larger than the width of the first portions along the second direction.
19. The method of claim 15, wherein the stacked structure comprises an upper conductive line and a lower conductive line, the upper conductive line is stacked on the lower conductive line, and at least one more first portion and second portion are connected at each end of the lower conductive line than a number of connective lines and second portions connected at each end of the upper conductive line.
20. The method of claim 15, wherein a length along the first direction of the first portions of the first flights of steps directly connected to the end of the stacked structure is greater than a length along the first direction of the first portions of the second flights of steps directly connected to the end of the stacked structure.
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December 21, 2022
August 20, 2024
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