Patentable/Patents/US-12087679
US-12087679

Package core assembly and fabrication methods

PublishedSeptember 10, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Patent Claims
6 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The semiconductor device assembly of claim 1, wherein the metal cladding layer comprises nickel.

3

3. The semiconductor device assembly of claim 1, wherein the metal cladding layer circumferentially surrounds the one or more conductive interconnections formed through the silicon core structure.

4

4. The semiconductor device assembly of claim 3, wherein the metal cladding layer is conductively coupled to ground by at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer.

5

5. The semiconductor device assembly of claim 3, wherein the metal cladding layer is conductively coupled to a reference voltage by at least one of the one or more conductive contacts formed on the first redistribution layer and the second redistribution layer.

6

6. The semiconductor device assembly of claim 1, wherein the dielectric layer comprises a flowable epoxy resin material.

8

8. The semiconductor device assembly of claim 7, wherein the dielectric layer has a thickness of between about 5 μm and about 50 μm.

Classification Codes (CPC)

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Patent Metadata

Filing Date

May 28, 2020

Publication Date

September 10, 2024

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Cite as: Patentable. “Package core assembly and fabrication methods” (US-12087679). https://patentable.app/patents/US-12087679

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