A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.
Legal claims defining the scope of protection, as filed with the USPTO.
6. The method of claim 1, wherein etching the bonded assembly to form an inter-wafer moat trench further comprises etching the bonded assembly to form the inter-wafer moat trench through the second semiconductor substrate and extending into the first semiconductor substrate, the method further comprising forming a protective material layer over the inter-wafer moat trench and on a sidewall of the first semiconductor substrate.
9. The method of claim 8, further comprising forming a cylindrical encapsulation dielectric layer over the cylindrical remaining portion of the bonded assembly prior to dicing the cylindrical remaining portion.
11. The method of claim 10, wherein removing the peripheral portion of the bonded assembly located outside the trench further comprises performing a blade-trimming process to cut off the peripheral portion of the second semiconductor substrate by a rotating blade.
16. The method of claim 15, further comprising forming through-substrate insulating spacers within each via cavity prior to forming the through-substrate via structure.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 23, 2022
September 10, 2024
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