An integrated circuit (IC) device includes a fin-type active region extending longitudinally in a first lateral direction on a substrate. A nanosheet is apart from a fin top surface of the fin-type active region in a vertical direction. An inner insulating spacer is between the substrate and the nanosheet. A gate line includes a main gate portion and a sub-gate portion. The main gate portion extends longitudinally in a second lateral direction on the nanosheet. The sub-gate portion is integrally connected to the main gate portion and between the substrate and the nanosheet. A source/drain region is in contact with the inner insulating spacer and the nanosheet. The source/drain region includes a single crystalline semiconductor body and at least one lower stacking fault surface linearly extending from the inner insulating spacer through the single crystalline semiconductor body.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The integrated circuit device as claimed in claim 1, wherein the at least one lower stacking fault surface includes a first lower stacking fault surface and a second lower stacking fault surface, which extend in directions that intersect with each other.
3. The integrated circuit device as claimed in claim 1, wherein the single crystalline semiconductor body includes single crystalline silicon doped with n-type impurities.
4. The integrated circuit device as claimed in claim 1, wherein the at least one lower stacking fault surface includes a first lower stacking fault surface having an angle of about 50° to about 60° with respect to a straight line in the first lateral direction.
5. The integrated circuit device as claimed in claim 1, wherein the at least one lower stacking fault surface includes a first lower stacking fault surface having an angle of about 30° to about 40° with respect to a straight line in the vertical direction.
6. The integrated circuit device as claimed in claim 1, wherein the at least one lower stacking fault surface is parallel to a {111} crystal plane of the single crystalline semiconductor body.
8. The integrated circuit device as claimed in claim 7, wherein the at least one upper stacking fault surface includes a first upper stacking fault surface having an angle of about 50° to about 60° with respect to a straight line in the first lateral direction.
9. The integrated circuit device as claimed in claim 7, wherein the at least one upper stacking fault surface includes a first upper stacking fault surface and a second upper stacking fault surface, which extend in directions that intersect with each other.
10. The integrated circuit device as claimed in claim 7, wherein the at least one upper stacking fault surface is parallel to a {111} crystal plane of the single crystalline semiconductor body.
14. The integrated circuit device as claimed in claim 12, wherein the plurality of stacking fault surfaces include a first stacking fault surface and a second stacking fault surface, which extend in directions that intersect with each other.
15. The integrated circuit device as claimed in claim 12, wherein an angle between at least one of the plurality of stacking fault surfaces and a straight line in the first lateral direction is in a range of about 50° to about 60°.
17. The integrated circuit device as claimed in claim 12, wherein at least one of the plurality of stacking fault surfaces is parallel to a {111} crystal plane of the single crystalline semiconductor body.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 23, 2021
September 10, 2024
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