A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The device of claim 1, wherein the memory is a level one (L1) cache.
6. The device of claim 1, wherein the instruction further specifies whether to perform extension on the set of table elements prior to storing in the destination register.
7. The device of claim 1, wherein the instruction specifies the set of indices by specifying a vector source index register that stores the set of indices.
8. The device of claim 1 further comprising a base address register configured to store a base address of the set of tables, wherein the instruction specifies the set of tables by specifying the base address register.
9. The device of claim 1 further comprising a configuration register configured to store a configuration of the set of tables, wherein the instruction specifies the configuration register.
10. The device of claim 9, wherein the configuration specifies a size of each of the set of data elements.
11. The device of claim 9, wherein the configuration specifies a size of each table of the set of tables.
12. The device of claim 9, wherein the configuration specifies a number of tables in the set of tables.
19. The method of claim 16, wherein the memory is a level one (L1) cache.
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September 26, 2022
September 17, 2024
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