Signal line structure, signal line driving method, and signal line circuit

2. The signal line structure according to claim 1, wherein the first level is a high level, and the second level is a low level.

3. The signal line structure according to claim 1, wherein the first driver or the second driver comprises at least one gating inverter, and the gating inverter is provided with an input terminal electrically connected to an input signal, an enable terminal connected to the first enable signal or the second enable signal, and an output terminal electrically connected to the signal line.

4. The signal line structure according to claim 1, wherein the plurality of parallel signal lines comprise odd data lines and even data lines arranged in a staggered manner, the odd data lines are configured to transmit odd signals obtained according to sampling of odd clocks, the even data lines are configured to transmit even signals obtained according to sampling of even clocks, and there is a phase difference of 180 degrees between the odd clock and the even clock; and the first enable signal corresponding to the odd data lines and the first enable signal corresponding to the even data lines have different phases, and the second enable signal corresponding to the odd data lines and the second enable signal corresponding to the even data lines have different phases.

5. The signal line structure according to claim 4, wherein there is a phase difference of 180 degrees between the first enable signal corresponding to the odd data lines and the first enable signal corresponding to the even data lines, and there is a phase difference of 180 degrees between the second enable signal corresponding to the odd data lines and the second enable signal corresponding to the even data lines.

7. The signal line driving method according to claim 6, wherein the first level is a high level, and the second level is a low level.