A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, further including depositing the encapsulant over a side surface of the semiconductor die.
3. The method of claim 1, further including depositing the encapsulant over a back surface of the semiconductor die.
4. The method of claim 1, further including disposing a solder bump on the under-bump metallization after depositing the encapsulant.
6. The method of claim 1, further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.
8. The method of claim 7, further including depositing the encapsulant over a side surface of the semiconductor die.
9. The method of claim 7, further including depositing the encapsulant over a back surface of the semiconductor die.
10. The method of claim 7, further including disposing a solder bump on the under-bump metallization after depositing the encapsulant.
12. The method of claim 7, further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.
14. The method of claim 13, further including depositing the encapsulant over a side surface of the semiconductor die.
15. The method of claim 13, further including depositing the encapsulant over a back surface of the semiconductor die.
17. The method of claim 13, further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.
19. The method of claim 18, further including depositing the encapsulant over a side surface of the semiconductor die.
20. The method of claim 18, further including depositing the encapsulant over a back surface of the semiconductor die.
22. The method of claim 18, further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 6, 2021
September 17, 2024
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