The present invention provides a semiconductor package structure including a first stacked structure and a second stacked structure, which is stacked on the first stacked structure. The first stacked structure includes a first dielectric layer, a first power chip, a first conductive connecting element, a first conductive pillar and a first patterned conductive layer. The second stacked structure includes a second dielectric layer, a second power chip, a second conductive connecting element, a second conductive pillar, a second patterned conductive layer, and a third patterned conductive layer. The first power chip and the second power chip are stacked to provide a smaller volume semiconductor package structure, that the first power chip and the second power chip may be directly electrically connected through the circuit structure and may eliminate the related disadvantages of the lead frame. In addition, a manufacturing method of a semiconductor package structure is also disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor package structure of claim 1, wherein the first electrode layout and the third electrode layout each comprises a drain and a gate, and the second electrode layout and the fourth electrode layout each comprises a source.
3. The semiconductor package structure of claim 1, wherein the first electrode layout and the third electrode layout each comprises a source, and the second electrode layout and the fourth electrode layout each comprises a drain and a gate.
4. The semiconductor package structure of claim 1, wherein the first patterned conductive layer comprises a patterned conductive layer and an external conductive pillar layer, which are stacked on top of each other and electrically connected, wherein the external conductive pillar layer has a columnar shape, and one end is exposed to the first surface of the first dielectric layer.
5. The semiconductor package structure of claim 1, further comprising: a control chip having an active surface and a non-active surface opposed to each other and embedded in the first dielectric layer and connected to the first patterned conductive layer with the non-active surface through the first conductive adhesive layer, wherein the active surface of the control chip is connected with the second patterned conductive layer through a plurality of first conductive connecting elements.
6. The semiconductor package structure of claim 1, further comprising: a control chip having an active surface and a non-active surface opposed to each other and embedded in the second dielectric layer and connected to the second patterned conductive layer with the non-active surface through the second conductive adhesive layer, wherein the active surface of the control chip is connected with the third patterned conductive layer through a plurality of second conductive connecting elements.
8. The manufacturing method of claim 7, wherein the first electrode layout and the third electrode layout each comprises a drain and a gate, and the second electrode layout and the fourth electrode layout each comprises a source.
9. The manufacturing method of claim 7, wherein the first electrode layout and the third electrode layout each comprises a source, and the second electrode layout and the fourth electrode layout each comprises a drain and a gate.
13. The manufacturing method of claim 12, wherein the first electrode layout and the third electrode layout each comprises a drain and a gate, and the second electrode layout and the fourth electrode layout each comprises a source.
14. The manufacturing method of claim 12, wherein the first electrode layout and the third electrode layout each comprises a source, and the second electrode layout and the fourth electrode layout each comprises a drain and a gate.
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November 16, 2021
September 24, 2024
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