Patentable/Patents/US-12100745
US-12100745

Dual metal capped via contact structures for semiconductor devices

PublishedSeptember 24, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

Patent Claims
7 claims

Legal claims defining the scope of protection, as filed with the USPTO.

4

4. The method of claim 3, wherein the removing the surface oxide from the top surface of the first metal capping layer comprises performing an argon plasma etch on the top surface of the first metal capping layer.

6

6. The method of claim 5, wherein the removing the surface oxide from the top surface of the via contact plug comprises performing a thermal annealing process in hydrogen.

7

7. The method of claim 1, wherein the interconnect structure comprises an additional metal different from the metal of the via contact plug.

8

8. The method of claim 1, further comprising forming a source/drain (S/D) contact structure on the fin structure, wherein the S/D contract structure is in contact with the first metal capping layer.

9

9. The method of claim 1, further comprising forming a gate contact structure above the fin structure, wherein the gate contract structure is in contact with the first metal capping layer.

10

10. The method of claim 1, wherein the via contact plug comprises ruthenium, the first and second metal capping layers comprise tungsten, and the interconnect structure comprises copper.

14

14. The method of claim 13, wherein the removing the surface oxide from the top surface of the first capping layer comprises performing an argon plasma etch on the top surface of the first metal capping layer.

Classification Codes (CPC)

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Patent Metadata

Filing Date

April 24, 2023

Publication Date

September 24, 2024

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Cite as: Patentable. “Dual metal capped via contact structures for semiconductor devices” (US-12100745). https://patentable.app/patents/US-12100745

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