A drive circuit, a method for driving the drive circuit and a memory are provided. The drive circuit includes a word line drive circuit and a first control circuit. The word line drive circuit includes an input terminal, an output terminal and at least one N-type transistor. The word line drive circuit is configured to provide an output signal to the output terminal according to an input signal received by the input terminal. The first control circuit is configured to pull down, in response to the input signal being a first control signal, a voltage of a substrate terminal of the at least one N-type transistor in the word line drive circuit, to reduce a leakage current of the at least one N-type transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The drive circuit of claim 1, wherein the third voltage is lower than zero voltage.
6. The drive circuit of claim 5, wherein a substrate terminal of the second N-type transistor is connected to the first electrode of the second P-type transistor.
8. The drive circuit of claim 7, wherein the level of the first control signal is lower than that of the second control signal.
10. The drive circuit of claim 9, wherein the fourth voltage is greater than the third voltage.
11. The drive circuit of claim 9, wherein the first electrode of the third N-type transistor is connected to the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor.
12. The drive circuit of claim 1, wherein the input terminal of the word line drive circuit is connected to a main word line, and the output terminal of the word line drive circuit is connected to a word line.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 27, 2022
October 15, 2024
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.