An interconnect structure is formed on a substrate in a semiconductor device. The interconnect structure includes a dielectric layer and a metal layer. The dielectric layer includes a region and a plurality of protrusions. The metal layer is disposed on the region and between the protrusions, wherein tops of the protrusions are exposed with respect to the metal layer. In a top view of the semiconductor device, the protrusions are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The interconnect structure of claim 1, wherein the region consists of rows of sub-regions extending in the direction and directly contiguous with each other, each row comprises one of the bent strips and one of the straight bars.
3. The interconnect structure of claim 2, wherein each of the bent strips is in direct contact with an edge of the row in which the bent strip is disposed.
4. The interconnect structure of claim 2, wherein the plurality of extension bars at each side are in direct contact with an edge of the row in which the straight bar is disposed.
5. The interconnect structure of claim 1, wherein the plurality of extension bars at the left side of the straight bars are aligned with each other in the second direction.
6. The interconnect structure of claim 1, wherein the plurality of extension bars at the right side of the straight bars are aligned with each other in the second direction.
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March 29, 2023
October 29, 2024
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