Implementations of a semiconductor substrate may include a wafer including a first side and a second side; and a support structure coupled to the wafer at a desired location on the first side, the second side, or both the first side and the second side. The support structure may include an organic compound.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor substrate of claim 1, wherein the wafer is not bonded to a carrier.
3. The semiconductor substrate of claim 1, wherein each opening of the plurality of openings comprises a perimeter having a closed shape.
4. The semiconductor substrate of claim 3, wherein the closed shape is circular.
5. The semiconductor substrate of claim 1, wherein the support structure comprises two or more strips coupled across the wafer.
6. The semiconductor substrate of claim 1, wherein the support structure comprises a plurality of intersecting strips comprised on the wafer.
7. The semiconductor substrate of claim 6, wherein the plurality of openings are comprised between the plurality of intersecting strips.
8. The semiconductor substrate of claim 1, wherein the wafer is exposed through the plurality of openings.
10. The semiconductor substrate of claim 9, wherein the plurality of strips comprise three or more substantially parallel strips.
11. The semiconductor substrate of claim 9, wherein the plurality of strips are intersecting.
12. The semiconductor substrate of claim 9, wherein the plurality of strips extend across an entire width of the uniformly thinned wafer.
13. The semiconductor substrate of claim 9, wherein the plurality of strips are angled relative to one another.
14. The semiconductor substrate of claim 9, wherein the plurality of strips extend across only a portion of a width of the uniformly thinned wafer.
15. The semiconductor substrate of claim 9, wherein the uniformly thinned wafer comprises a notch exposed between the plurality of strips.
17. The semiconductor substrate of claim 16, wherein the plurality of intersecting strips form a plurality of substantially rectangular openings through the support structure.
18. The semiconductor substrate of claim 16, further comprising an edge exclusion region, wherein the plurality of intersecting strips extend to an inner perimeter of the edge exclusion region.
19. The semiconductor substrate of claim 16, wherein the plurality of intersecting strips extend across an entire width of the uniformly thinned wafer.
20. The semiconductor substrate of claim 16, wherein the plurality of intersecting strips comprise at least three substantially parallel strips.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 13, 2023
October 29, 2024
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