Patentable/Patents/US-12132079
US-12132079

Bonding and isolation techniques for stacked transistor structures

PublishedOctober 29, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.

Patent Claims
6 claims

Legal claims defining the scope of protection, as filed with the USPTO.

4

4. The method of claim 1, wherein the first plasma-activated surface of the first insulation layer and the second plasma-activated surface of the second insulation layer are a first silanol surface and a second silanol surface, respectively.

5

5. The method of claim 1, wherein a thickness of the isolation structure is less than about 10 nm, a thickness of the first insulation layer is less than about 5 nm, and a thickness of the second insulation layer is less than about 5 nm.

6

6. The method of claim 1, further comprising cleaning the first plasma-activated surface of the first insulation layer and the second plasma-activated surface of the second insulation layer with a deionized water rinse before the bonding.

12

12. The method of claim 10, wherein a thickness of the isolation structure is less than about 10 nm, a thickness of the first insulation layer is less than about 5 nm, and a thickness of the second insulation layer is less than about 5 nm.

17

17. The method of claim 16, wherein the first nitride layer is a first silicon nitride layer, and the second nitride layer is a second silicon nitride layer.

18

18. The method of claim 16, wherein the first nitride layer is a first boron nitride layer, and the second nitride layer is a second boron nitride layer.

Classification Codes (CPC)

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Patent Metadata

Filing Date

December 21, 2023

Publication Date

October 29, 2024

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Cite as: Patentable. “Bonding and isolation techniques for stacked transistor structures” (US-12132079). https://patentable.app/patents/US-12132079

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