A semiconductor memory device includes a memory cell array (MCA) and a pass transistor unit (PTU). The MCA includes memory block(s) that has source selection line(s) (SSL), word lines (WLs), drain selection line(s) (DSL), and dummy WL(s) (DWL). The PTU includes source pass transistor(s) to selectively transmit a source driving signal (source DS) to the SSL, memory pass transistors (MPTs) to selectively transmit a WL DS to the WLs, respectively, drain pass transistor(s) (PT) to selectively transmit a drain DS to the DSL, and dummy PT(s) to selectively transmit a DWL DS to the DWL. The source DS, the WL DS, the drain DS, and the DWL DS may each be associated with a respective voltage range. Sizes of the source PT, the MPTs, the drain PT, and the dummy PTs are set based on the respective voltage ranges.
Legal claims defining the scope of protection, as filed with the USPTO.
4. The semiconductor memory device according to claim 1, wherein the sizes of the source pass transistor, the plurality of memory pass transistors, the drain pass transistor, and the at least one dummy pass transistor include areas of active regions in which the source pass transistor, the plurality of memory pass transistors, the drain pass transistor, and the at least one dummy pass transistor are respectively formed.
5. The semiconductor memory device according to claim 1, wherein the sizes of the source pass transistor, the plurality of memory pass transistors, the drain pass transistor, and the at least one dummy pass transistor include gate widths of source pass transistor, the plurality of memory pass transistors, the drain pass transistor, and the at least one dummy pass transistor.
6. The semiconductor memory device according to claim 1, wherein at least two of the respective voltage ranges are independent of each other.
7. The semiconductor memory device according to claim 1, wherein each of the respective voltage ranges is different from the others of the respective voltage ranges.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 18, 2022
October 29, 2024
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