A memory controller receives a command to program information to a memory storage array controlled by the memory controller. The memory controller determines a target memory state to store the information, and a target threshold voltage level corresponding to the target memory state. Based at least on the target memory state, the memory controller determines one or more program pulses for a pre-program cycle, including voltage levels for the one or more program pulses based at least on the target threshold voltage level. The memory controller selects a memory location in the memory storage array to program the information, and pre-programs the selected memory location by applying the one or more program pulses at respective voltage levels, the one or more program pulses applied without program verify operations. Following the pre-programming, the memory controller programs the information to the selected memory location.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein programming the information to the selected memory location comprises applying one or more additional program pulses to the selected memory location to reach the second target voltage level, the one or more additional program pulses applied with respective accompanying program verify operations.
8. The memory device of claim 7, wherein programming the information to the selected memory location comprises applying one or more additional program pulses to the selected memory location to reach the second target voltage level, the one or more additional program pulses applied with respective accompanying program verify operations.
14. The memory controller of claim 13, wherein programming the information to the selected memory location comprises applying one or more additional program pulses to the selected memory location to reach the second target voltage level, the one or more additional program pulses applied with respective accompanying program verify operations.
21. The method of claim 19, wherein the voltage levels for the one or more program pulses are determined to be within a specified range of the target threshold voltage level that is less than the target threshold voltage level such that a threshold voltage of the selected memory location upon completion of the pre-programming is less than the target threshold voltage level and within the specified range of the target threshold voltage level.
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August 5, 2021
November 5, 2024
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